Patents by Inventor Chih Chao Chen
Chih Chao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11996483Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.Type: GrantFiled: December 14, 2022Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
-
Publication number: 20240160844Abstract: The present disclosure provides a synonym searching method, which includes steps as follows. When receiving the vocabulary and the definition of the vocabulary from the user device, the natural language processing model is used to search the synonym of the vocabulary from the data governance dictionary according to the definition of the vocabulary; after providing the synonym to the user device, feedback information about the synonym is received from the user device, and the feedback information is used as the token of the vocabulary for the natural language processing model.Type: ApplicationFiled: February 8, 2023Publication date: May 16, 2024Inventors: Wei-Chao CHEN, Chen-I HUANG, Yu-Lun CHANG, Chuo-Jui WU, Chih-Pin WEI
-
Publication number: 20240163075Abstract: The present disclosure provides a privacy computing method based on homomorphic encryption, which includes steps as follows. The ciphertext data is received, where the ciphertext data has a floating-point homomorphic encryption data structure, and the floating-point homomorphic encryption data structure of the ciphertext data includes the ciphertext mantissa, exponent parameter and gain parameter. The gain parameter sets the precision of the floating point corresponding to the ciphertext mantissa. The exponent parameter is adapted to multiplication or division. The artificial intelligence model performs operations on the ciphertext data to return the ciphertext result.Type: ApplicationFiled: February 17, 2023Publication date: May 16, 2024Inventors: Yu Te KU, Chih-Fan HSU, Wei-Chao CHEN, Feng-Hao LIU, Ming-Ching CHANG
-
Publication number: 20240161158Abstract: The present disclosure proposes a service plan automatic generation system and operation method thereof. The operation method includes a method for generating standardized items based on a service record, which includes the following steps: analyzing multiple instances to generate multiple feature tags, generating multiple word frequency vectors corresponding to the feature tags according to the instances, and performing an aggregation procedure for a plurality of times. Each time performing the aggregation procedure includes: executing a clustering algorithm to divide multiple instances into multiple groups, analyzing multiple variable parts and an identical part of multiple feature vectors in each group, outputting the variable parts as feature tag sets, and using the identical part as an index of the group, when a stop condition is detected, the index generated by the aggregation procedure in the last time is outputted as a standardized item.Type: ApplicationFiled: March 1, 2023Publication date: May 16, 2024Inventors: Yu-Lun Chang, Wei-Chao Chen, Chih-Pin Wei, Yao Yu Chung, Ying Chieh Kung, Yu Chang Chang
-
Publication number: 20240154972Abstract: A method for permission management includes: generating a plurality of job roles with different permissions according to organization permission table; generating first permission structure directed graph according to the job roles; selecting one of the job roles in first permission structure directed graph as target job role; generating minimum directed spanning graph in first permission structure directed graph according to target job role; determining whether permission of each of the job roles in first permission structure directed graph matches job of each of the job roles in first permission structure directed graph; and adjusting permission and job of each of the job roles to generate second permission structure directed graph if it is determined that permission of each of the job roles in first permission structure directed graph does not match job of each of the job roles in first permission structure directed graph.Type: ApplicationFiled: December 21, 2022Publication date: May 9, 2024Inventors: Wei-Chao CHEN, Ming-Chi CHANG, Chih-Pin WEI, Chuo-Jui WU
-
Publication number: 20240105827Abstract: A semiconductor structure includes a first channel layer and a first barrier layer on the first channel layer. The first channel layer has a first potential well adjacent to the interface between the first channel layer and the first barrier layer. The semiconductor structure further includes a second channel layer on the first barrier layer, a second barrier layer on the second channel layer, and an intermediate layer between the second channel layer and the second barrier layer. The second channel layer has a second potential well adjacent to the interface between the second channel layer and the intermediate layer. The intermediate layer has a greater energy gap than either the first barrier layer or the second barrier layer. The energy gap of the first barrier layer is no less than the energy gap of the second barrier layer.Type: ApplicationFiled: July 25, 2023Publication date: March 28, 2024Inventors: Chih-Hao CHEN, Yi-Ru SHEN, Yi-Chao LIN
-
Publication number: 20240099148Abstract: A semiconductor device is provided. The semiconductor device includes a memory including a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and an upper electrode on the MTJ stack. The semiconductor device also includes at least one dielectric layer formed around the memory, wherein a top metal layer contact hole is formed in the at least one dielectric layer, a dielectric liner layer formed in the top metal contact hole, and a top metal layer contact in the top metal layer contact hole.Type: ApplicationFiled: September 16, 2022Publication date: March 21, 2024Inventors: Hsueh-Chung Chen, Koichi Motoyama, Chanro Park, Yann Mignot, Chih-Chao Yang
-
Publication number: 20240087057Abstract: A power consumption monitoring device includes a sensor, a storage, and a processor. The sensor is configured to detect a power-consuming device quantity and a power consumption amount. The storage is configured to store the power-consuming device quantity and the power consumption amount. The processor is communicatively connected to the sensor and the storage. The processor is configured to calculate a power-consuming device idling indicator based on the power-consuming device quantity and the power consumption amount in a monitoring time interval, wherein the power-consuming device idling indicator is used for indicating a deviation status of the power-consuming device quantity and the power consumption amount. The processor is further configured to determine whether the power-consuming device idling indicator exceeds a warning threshold. In response to the power-consuming device idling indicator exceeding the warning threshold, the processor is further configured to generate a warning message.Type: ApplicationFiled: December 20, 2022Publication date: March 14, 2024Inventors: Wei-Chao CHEN, Ming-Chi CHANG, Chih-Pin WEI, Ke-Li WU, Hua-Hsiu CHIANG, Yu-Lun CHANG
-
Publication number: 20240080180Abstract: The federated learning system includes a moderator and client devices. Each client device performs a method for verifying model update as follows: receiving a hash function and a general model; training a client model according to the general model and raw data; calculating a difference as an update parameter between the general model and the client model, sending the update parameter to the moderator; inputting the update parameter to the hash function to generate a hash value; sending the hash value to other client devices, and receiving other hash values; summing all the hash values to generate a trust value; receiving an aggregation parameter calculated according to the update parameters; inputting the aggregation parameter to the hash function to generate a to-be-verified value; and updating the client model according to the aggregation parameter when the to-be-verified value equals the trust value.Type: ApplicationFiled: December 20, 2022Publication date: March 7, 2024Inventors: Chih-Fan HSU, Wei-Chao CHEN, Jing-Lun Huang, Ming-Ching Chang, Feng-Hao Liu
-
Publication number: 20240078170Abstract: A setting method of in-memory computing simulator includes: performing a plurality of test combinations by an in-memory computing device and recording a plurality of first estimation indices corresponding to the plurality of test combinations respectively, wherein each of the plurality of test combinations includes one of a plurality of neural network models and one of a plurality of datasets, executing a simulator according to the plurality of test combinations by a processing device and recording a plurality of second estimation indices corresponding to the plurality of test combinations respectively, wherein the simulator has a plurality of adjustable settings; calculating a correlation sum according to the plurality of first estimation indices and the plurality of second estimation indices by the processing device, and performing an optimal algorithm to search an optimal parameter in the setting space constructed by the plurality of settings so that the correlation sum is maximal.Type: ApplicationFiled: November 21, 2022Publication date: March 7, 2024Inventors: Ke-Han Li, Chih-Fan Hsu, Yu-Sheng Lin, Wei-Chao CHEN
-
Patent number: 11923405Abstract: The present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, an insulating layer disposed on the substrate, a first conductive feature disposed in the insulating layer, and a capacitor structure disposed on the insulating layer. The capacitor structure includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked. The semiconductor device also includes a first via connected to the first electrode and the third electrode, a second via connected to the second electrode, and a third via connected to the first conductive feature. A part of the first via is disposed in the insulating layer. A portion of the first conductive feature is directly under the capacitor structure.Type: GrantFiled: May 23, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Chih-Fan Huang, Hung-Chao Kao, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hsiang-Ku Shen, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
-
Patent number: 10324505Abstract: A heat dissipation assembly includes a pressing unit and a heat dissipation module. The pressing unit includes a pressing plate, a plurality of elastic cantilevers and contacting members. The pressing plate can be secured on a bottom plate so that a heat source can be sandwiched between the pressing plate and the bottom plate. The elastic cantilevers are respectively disposed on the pressing plate and protruded outwards from the pressing plate to be suspended in midair. The contacting members are respectively disposed on the elastic cantilevers for abutting the bottom plate. The heat dissipation module is fixedly connected to the pressing plate and a carrier member for thermally guiding the heat source.Type: GrantFiled: April 13, 2017Date of Patent: June 18, 2019Assignee: Quanta Computer Inc.Inventors: Chih-Chao Chen, Pei-Yu Chang, Chia-Hung Ma, Chih-Wei Jen
-
Publication number: 20180192546Abstract: A heat dissipation assembly includes a pressing unit and a heat dissipation module. The pressing unit includes a pressing plate, a plurality of elastic cantilevers and contact members. The pressing plate can be secured on a bottom plate so that a heat source can be sandwiched between the pressing plate and the bottom plate. The elastic cantilevers are respectively disposed on the pressing plate and protruded outwards from the pressing plate to be suspended in midair. The contact members are respectively disposed on the elastic cantilevers for abutting the bottom plate. The heat dissipation module is fixedly connected to the pressing plate and a carrier member for thermally guiding the heat source.Type: ApplicationFiled: April 13, 2017Publication date: July 5, 2018Inventors: Chih-Chao Chen, Pei-Yu Chang, Chia-Hung Ma, Chih-Wei Jen
-
Patent number: 8203092Abstract: A keypad structure with a backlight source includes a base, a light guiding plate, a thin film circuit board, a resilient component, a keycap, and an elevating mechanism. The thin film circuit board includes at least one exhausting notch for increasing exhaust as the resilient component is compressed. A plurality of microstructures is formed on the light guiding plate, and the keypad structure further includes a transparent layer formed on the keycap. Light emitted from the backlight source and refracted by the plurality of microstructures passes through the keycap and the transparent layer as the backlight source lights the lateral side of the light guiding plate, so as to illuminate the transparent layer. Thus, the present invention has advantages of illuminating pattern, regional illumination, and preferable comfort.Type: GrantFiled: July 13, 2010Date of Patent: June 19, 2012Assignee: Ichia Technologies, Inc.Inventor: Chih-Chao Chen
-
Patent number: 8027551Abstract: A reconfigurable image processor for image processing includes an arithmetic module, a first memory unit, a bus control module and a connecting module. By setting different configurations or configuring connections among arithmetic units via the connecting module, the operations of arithmetic units are reconfigured to include different functions. The present invention provides an application architecture including a sensor module, a display module, a second memory unit and a reconfigurable image processor.Type: GrantFiled: June 1, 2007Date of Patent: September 27, 2011Assignee: Vivotek Inc.Inventors: Shao Yi Chien, Chih Chao Chen, Chun Fu Shen, Wan Kuei Lin
-
Publication number: 20110219964Abstract: A method of making a keycap structure having a UV-cured resin and making a keyboard having such keycap structures, in which a film is printed with a top color layer and then a bottom color layer, the film is hot-pressed to form a thin shell, a UV-cured resin layer is formed on the bottom color layer through a UV-curing process, and finally the film having the UV-cured resin layer is cut or punched out to form a plurality of keycap structures. A keyboard including keycap structures having a UV-cured resin may be further formed by combining the keycap structures and a set of keyboard members.Type: ApplicationFiled: July 13, 2010Publication date: September 15, 2011Inventor: Chih-Chao Chen
-
Publication number: 20110219965Abstract: A method of making a keycap structure and making a keyboard having keycap structures, in which a film is printed with a top color layer and then a bottom color layer, the film is hot-pressed to form a thin shell, a plastic injection layer is formed on the bottom color layer by a plastic injection molding process, and finally the film having the plastic injection layer is cut or punched out to form a plurality of keycap structures. A keyboard having keycap structures may be further formed by combining the keycap structures and a set of keyboard members.Type: ApplicationFiled: July 13, 2010Publication date: September 15, 2011Inventor: Chih-Chao Chen
-
Publication number: 20110220477Abstract: A keypad structure with a backlight source includes a base, a light guiding plate, a thin film circuit board, a resilient component, a keycap, and an elevating mechanism. The thin film circuit board includes at least one exhausting notch for increasing exhaust as the resilient component is compressed. A plurality of microstructures is formed on the light guiding plate, and the keypad structure further includes a transparent layer formed on the keycap. Light emitted from the backlight source and refracted by the plurality of microstructures passes through the keycap and the transparent layer as the backlight source lights the lateral side of the light guiding plate, so as to illuminate the transparent layer. Thus, the present invention has advantages of illuminating pattern, regional illumination, and preferable comfort.Type: ApplicationFiled: July 13, 2010Publication date: September 15, 2011Inventor: Chih-Chao Chen
-
Publication number: 20110223352Abstract: A method of making a keycap structure including steps of colored plastic body formation, final coating spraying, baking, laser engraving, transparent layer covering, and finishing. Through the aforesaid steps, at least a colored plastic body is pre-formed. The colored plastic body has a to-be-processed surface. The to-be-processed surface is spray-coated with a final coating. The colored plastic body and the final coating are baked to allow the final coating to harden on the to-be-processed surface. The final coating is processed by a laser beam to format least a hollowed portion. The hollowed portion of the final coating and the correspondingly exposed to-be-processed surface together constitute at least a pattern portion. The pattern portion and the final coating are covered with a transparent layer to protect the pattern portion and the final coating, and a keycap structure is finished from the colored plastic body.Type: ApplicationFiled: July 13, 2010Publication date: September 15, 2011Inventor: Chih-Chao Chen
-
Publication number: 20080114974Abstract: A reconfigurable image processor for image processing includes an arithmetic module, a first memory unit, a bus control module and a connecting module. By setting different configurations or configuring connections among arithmetic units via the connecting module, the operations of arithmetic units are reconfigured to include different functions. The present invention provides an application architecture including a sensor module, a display module, a second memory unit and a reconfigurable image processor.Type: ApplicationFiled: June 1, 2007Publication date: May 15, 2008Inventors: Shao Yi Chien, Chih Chao Chen, Chun Fu Shen, Wan Kuei Lin