Patents by Inventor Chih-Cheh Chen
Chih-Cheh Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230214326Abstract: A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.Type: ApplicationFiled: June 1, 2021Publication date: July 6, 2023Inventors: Jordan HORWICH, Jerry ALSTON, Chih-Cheh CHEN, Patrick LEE, Scott MILTON, Jeekyoung PARK
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Patent number: 11500797Abstract: A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.Type: GrantFiled: June 1, 2021Date of Patent: November 15, 2022Assignee: Netlist, Inc.Inventors: Jordan Horwich, Jerry Alston, Chih-Cheh Chen, Patrick Lee, Scott Milton, Jeekyoung Park
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Publication number: 20210374080Abstract: A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.Type: ApplicationFiled: June 1, 2021Publication date: December 2, 2021Inventors: Jordan HORWICH, Jerry ALSTON, Chih-Cheh CHEN, Patrick LEE, Scott MILTON, Jeekyoung PARK
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Patent number: 10929330Abstract: Examples may include chipsets, processor circuits, and a system including chipsets and processor circuits. The chipsets and processor circuits can be coupled together via side band interconnect. The chipsets and processor circuits can be coupled together dynamically, during runtime using the side band interconnects. A chipset can send control signals for other chipsets and/or receive control signals from processor circuits via the side band links to dynamically coordinate the chipsets and processor circuits into systems.Type: GrantFiled: June 30, 2017Date of Patent: February 23, 2021Assignee: INTEL CORPORATIONInventors: Chih-Cheh Chen, Russell J. Wunderlich, Tina C. Zhong
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Patent number: 10817454Abstract: An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.Type: GrantFiled: April 26, 2019Date of Patent: October 27, 2020Assignee: Intel CorporationInventors: Chih-Cheh Chen, Janusz P. Jurski, Amit Kumar Srivastava, Malay Trivedi, James Mitchell, Piotr Michael Kwidzinski, David N. Lombard
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Patent number: 10620966Abstract: Embodiments disclosed herein relate to coordinated system boot and reset flows and improve reliability, availability, and serviceability (RAS) among multiple chipsets. In an example, a system includes a master chipset having multiple interfaces, each interface to connect to one of a processor and a chipset, at least one processor connected to the master chipset, at least one non-master chipset connected to the master chipset, and a sideband messaging channel connecting the master chipset and the non-master chipsets, wherein the master chipset is to probe a subset of its multiple interfaces to discover a topology of connected processors and non-master chipsets, and use the sideband messaging channel to coordinate a synchronized boot flow.Type: GrantFiled: September 28, 2017Date of Patent: April 14, 2020Assignee: Intel CorporationInventors: Tina C. Zhong, Russell J. Wunderlich, Chih-Cheh Chen, Malay Trivedi
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Publication number: 20190251055Abstract: An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.Type: ApplicationFiled: April 26, 2019Publication date: August 15, 2019Applicant: Intel CorporationInventors: Chih-Cheh Chen, Janusz P. Jurski, Amit Kumar Srivastava, Malay Trivedi, James Mitchell, Piotr Michael Kwidzinski, David N. Lombard
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Publication number: 20190095224Abstract: Embodiments disclosed herein relate to coordinated system boot and reset flows and improve reliability, availability, and serviceability (RAS) among multiple chipsets. In an example, a system includes a master chipset having multiple interfaces, each interface to connect to one of a processor and a chipset, at least one processor connected to the master chipset, at least one non-master chipset connected to the master chipset, and a sideband messaging channel connecting the master chipset and the non-master chipsets, wherein the master chipset is to probe a subset of its multiple interfaces to discover a topology of connected processors and non-master chipsets, and use the sideband messaging channel to coordinate a synchronized boot flow.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Inventors: Tina C. Zhong, Russell J. Wunderlich, Chih-Cheh Chen, Malay Trivedi
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Publication number: 20190004989Abstract: Examples may include chipsets, processor circuits, and a system including chipsets and processor circuits. The chipsets and processor circuits can be coupled together via side band interconnect. The chipsets and processor circuits can be coupled together dynamically, during runtime using the side band interconnects. A chipset can send control signals for other chipsets and/or receive control signals from processor circuits via the side band links to dynamically coordinate the chipsets and processor circuits into systems.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Applicant: INTEL CORPORATIONInventors: Chih-Cheh Chen, Russell J. Wunderlich, Tina C. Zhong
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Patent number: 8908688Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.Type: GrantFiled: September 11, 2012Date of Patent: December 9, 2014Assignee: Intel CorporationInventors: Chih-Cheh Chen, Michael T. Klinglesmith, David M. Lee, John Zulauf, Itay Franko, Peter J. Elardo, Mohan K. Nair, Chris Van Beek
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Publication number: 20130016720Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.Type: ApplicationFiled: September 11, 2012Publication date: January 17, 2013Inventors: Chih-Cheh Chen, Michael T. Klinglesmith, David M. Lee, John Zulauf, Itay Franko, Peter J. Elardo, Mohan K. Nair, Christopher Van Beek
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Patent number: 8270405Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.Type: GrantFiled: June 30, 2009Date of Patent: September 18, 2012Assignee: Intel CorporationInventors: Chih-Cheh Chen, Michael T. Klinglesmith, David M. Lee, John Zulauf, Itay Franko, Peter J. Elardo, Mohan K. Nair, Christopher Van Beek
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Publication number: 20100329254Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.Type: ApplicationFiled: June 30, 2009Publication date: December 30, 2010Applicant: INTEL CORPORATIONInventors: Chih-Cheh Chen, Michael T. Klinglesmith, David M. Lee, John Zulauf, Itay Franko, Peter J. Elardo, Mohan K. Nair, Christopher Van Beek
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Patent number: 6298420Abstract: Method and apparatus for processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.Type: GrantFiled: May 8, 2000Date of Patent: October 2, 2001Assignee: Intel CorporationInventors: Suresh Chittor, Chih-Cheh Chen, Sin Sim Tan, Jonathan Nick Spitz
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Patent number: 6061764Abstract: Method and apparatus for processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.Type: GrantFiled: January 26, 1998Date of Patent: May 9, 2000Assignee: Intel CorporationInventors: Suresh Chittor, Chih-Cheh Chen, Sin Sim Tan, Jonathan Nick Spitz