Patents by Inventor Chih-Chen Hsueh

Chih-Chen Hsueh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150046447
    Abstract: A controlling method of a multimedia player device is disclosed. The multimedia player device is capable of playing plural multimedia files from plural memory cards. The controlling method comprising: when a memory card of the memory cards is connected to the multimedia player device, determining if there is a corresponding log file corresponding to the connected memory card; if the log file exists, creating a playlist comprising at least part of the plural multimedia files according to the log file; and, playing the multimedia files according to the playlist from the connected memory card.
    Type: Application
    Filed: August 6, 2013
    Publication date: February 12, 2015
    Applicant: Transcend Information, Inc.
    Inventors: Chih-Chen HSUEH, Kuan-Jen CHEN
  • Patent number: 8716802
    Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: May 6, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor Chiang Liang, You-Ren Liu, Chih-Chen Hsueh
  • Patent number: 8637936
    Abstract: A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: January 28, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Ling Chiu, Victor-Chiang Liang, Chih-Yu Tseng, Kun-Szu Tseng, Cheng-Wen Fan, Hsin-Kai Chiang, Chih-Chen Hsueh
  • Publication number: 20110073957
    Abstract: A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures.
    Type: Application
    Filed: September 25, 2009
    Publication date: March 31, 2011
    Inventors: Kai-Ling Chiu, Victor-Chiang Liang, Chih-Yu Tseng, Kun-Szu Tseng, Cheng-Wen Fan, Hsin-Kai Chiang, Chih-Chen Hsueh
  • Publication number: 20100320540
    Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.
    Type: Application
    Filed: August 9, 2010
    Publication date: December 23, 2010
    Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor Chiang Liang, You-Ren Liu, Chih-Chen Hsueh
  • Patent number: 7804154
    Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: September 28, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor Chiang Liang, You-Ren Liu, Chih-Chen Hsueh
  • Patent number: 7803687
    Abstract: A method for forming a thin film resistor includes providing a substrate having a transistor region and a thin film resistor region defined thereon, sequentially forming a dielectric layer, a metal layer and a first hard mask layer on the substrate, patterning the first hard mask layer to form at least a thin film resistor pattern in the thin film resistor region, sequentially forming a polysilicon layer and a second hard mask layer on the substrate, patterning the second hard mask layer to form at least a gate pattern in the transistor region, and performing an etching process to form a gate and a thin film resistor respectively in the transistor region and the thin film resistor region.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: September 28, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor-Chiang Liang, You-Ren Liu, Chih-Chen Hsueh
  • Publication number: 20100148263
    Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 17, 2010
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: KAI-LING CHIU, CHIH-YU TSENG, VICTOR CHIANG LIANG, YOU-REN LIU, Chih-Chen Hsueh
  • Publication number: 20100099229
    Abstract: A method for forming a thin film resistor includes providing a substrate having a transistor region and a thin film resistor region defined thereon, sequentially forming a dielectric layer, a metal layer and a first hard mask layer on the substrate, patterning the first hard mask layer to form at least a thin film resistor pattern in the thin film resistor region, sequentially forming a polysilicon layer and a second hard mask layer on the substrate, patterning the second hard mask layer to form at least a gate pattern in the transistor region, and performing an etching process to form a gate and a thin film resistor respectively in the transistor region and the thin film resistor region.
    Type: Application
    Filed: October 17, 2008
    Publication date: April 22, 2010
    Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor-Chiang Liang, You-Ren Liu, Chih-Chen Hsueh