Patents by Inventor Chih-Cheng Chen

Chih-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10385443
    Abstract: A device for growing large-sized monocrystalline crystals, including a crucible adapted to grow crystals from a material source and with a seed crystal and including therein a seed crystal region, a growth chamber, and a material source region; a thermally insulating material disposed outside the crucible and below a heat dissipation component; and a plurality of heating components disposed outside the thermally insulating material to provide heat sources, wherein the heat dissipation component is of a heat dissipation inner diameter and a heat dissipation height which exceeds a thickness of the thermally insulating material.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: August 20, 2019
    Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Dai-Liang Ma, Hsueh-I Chen, Bo-Cheng Lin, Cheng-Jung Ko, Ying-Cong Zhao, Chih-Wei Kuo, Shu-Yu Yeh
  • Publication number: 20190247522
    Abstract: A biocompatible magnetic material containing an iron oxide nanoparticle and one or more biocompatible polymers, each having formula (I) below, covalently bonded to the iron oxide nanoparticle: in which each of variables R, L, x, and y is defined herein, the biocompatible magnetic material contains 4-15% Fe(II) ions relative to the total iron ions. Also disclosed in a method of preparing the biocompatible magnetic material.
    Type: Application
    Filed: November 29, 2018
    Publication date: August 15, 2019
    Inventors: Wen-Yuan Hsieh, Yuan-Hung Hsu, Chia-Wen Huang, Ming-Cheng Wei, Chih-Lung Chen, Shian-Jy Wang
  • Patent number: 10373964
    Abstract: A method, of writing to a memory cell, includes: causing a pulling device of the memory cell to pull a voltage level at a first data node of the memory cell toward a first supply voltage level responsive to a voltage level at a second data node of the memory cell; causing a pass gate of the memory cell to pull the voltage level at the first data node of the memory cell toward a second supply voltage level responsive to a word line signal, the second supply voltage level being different from the first supply voltage level; and limiting a driving capability of the pulling device by a resistive device, the resistive device being electrically coupled between the pulling device and a supply voltage source configured to provide a first supply voltage, the first supply voltage having the first supply voltage level.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: August 6, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Huei Chen, Hung-Jen Liao, Chih-Yu Lin, Jonathan Tsung-Yung Chang, Wei-Cheng Wu
  • Patent number: 10371967
    Abstract: Provided is an eyewear lens, including a lens substrate and an optical interference coating; the lens substrate is comprised of an optical material, and the optical interference coating is bonded to the lens substrate and is stacked by the composition of high and low reflectivity materials. A predefined reflective appearance color will be formed by light getting through the optical interference coating. The lens substrate contains another filter on one side surface or both side surfaces or inside the lens substrate which is complementary to the light after penetrating the optical interference coating such that the overall transmittance light tone remain neutral balance. The overall transmittance light spectrum has three pass-bands corresponding to the maximum response of the human eye cone cells, and the relatively high transmittance values of each pass-band center are approximately at 450 nm, 530 nm and 610 nm. The FWHM of each pass-band is between 3 nm and 50 nm.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: August 6, 2019
    Assignee: HWA MEEI OPTICAL CO., LTD.
    Inventors: Charles Cheng, Chih Ming Chen
  • Publication number: 20190236326
    Abstract: A fingerprint sensor includes a die, a plurality of conductive structures, an encapsulant, a plurality of conductive patterns, a first dielectric layer, a second dielectric layer, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The conductive patterns are over the die and are electrically connected to the die and the conductive structures. Top surfaces of the conductive patterns are flat. The first dielectric layer is over the die and the encapsulant. A top surface of the first dielectric layer is coplanar with top surfaces of the conductive patterns. The second dielectric layer covers the first dielectric layer and the conductive patterns. The redistribution structure is over the rear surface of the die.
    Type: Application
    Filed: January 30, 2018
    Publication date: August 1, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ying-Cheng Tseng
  • Patent number: 10366200
    Abstract: A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes generating a first layout of the integrated circuit based on design criteria, generating a standard cell layout of the integrated circuit, generating a via color layout of the integrated circuit based on the first layout and the standard cell layout and performing a color check on the via color layout based on design rules. The first layout having a first set of vias arranged in first rows and first columns. The standard cell layout having standard cells and a second set of vias arranged in the standard cells. The via color layout having a third set of vias. The third set of vias including a portion of the second set of vias and corresponding locations, and color of corresponding sub-set of vias.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Lin, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shih-Wei Peng, Wei-Chen Chien
  • Patent number: 10367079
    Abstract: A semiconductor device includes a substrate having a fin projecting upwardly through an isolation structure over the substrate; a gate stack over the isolation structure and engaging the fin; and a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack. The semiconductor device further includes a first dielectric layer vertically between the fin and the gate spacer and in physical contact with the sidewall of the gate stack, wherein the first dielectric layer has a laterally extending cavity. The semiconductor device further includes a second dielectric layer filling in the cavity, wherein the first and second dielectric layers include different materials.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Cheng Chang, Jr-Jung Lin, Shih-Hao Chen, Chih-Han Lin, Mu-Tsang Lin, Yung Jung Chang
  • Publication number: 20190229120
    Abstract: In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Kuo-Cheng CHING, Chih-Hao WANG, Chih-Liang CHEN, Shi Ning JU
  • Publication number: 20190209706
    Abstract: A composition for improving the solubility of poorly soluble substances is provided. The composition includes about 40-99.5% by weight of cyclodextrin and/or derivatives thereof; about 0.05-10% by weight of at least one water-soluble polymer; and about 0.05-60% by weight of at least one water-soluble stabilizer.
    Type: Application
    Filed: December 26, 2018
    Publication date: July 11, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Wen-Chia HUANG, Yen-Jen WANG, Felice CHENG, Chia-Ching CHEN, Shao-Chan YIN, Chien-Lin PAN, Tsan-Lin HU, Meng-Nan LIN, Kuo-Kuei HUANG, Maggie LU, Chih-Peng LIU
  • Patent number: 10349542
    Abstract: The present disclosure provides a latch assembly for securing an electronic component within a computing device. The latch assembly includes a latch, a base, and a cover. The latch includes a first structural member with a first plurality of pins; a second structural member with a second plurality of pins; at least one linking element that connects the first structural member with the second structural member; and a first securing element located at the first structural member. The base includes a receiving space for receiving the latch; a first plurality of slots configured to receive the first plurality of pins; a second plurality of slots configured to receive the second plurality of pins; a plurality of protruding elements; and a second securing element corresponding with the first securing element. The cover is secured to the base at the plurality of protruding elements.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: July 9, 2019
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Jung Chen, Chih-Hsiang Lee, Kun-Pei Liu, Tsung-Cheng Lin
  • Publication number: 20190207364
    Abstract: A laser driver device is provided, which includes a control circuit, a driver circuit and a feedback circuit. The control circuit receives setup data and convert the setup data into a setup signal. The driver circuit receives the setup signal and generates a drive current according to the setup signal to drive a laser light source. The feedback circuit receives the setup data and the feedback signal of the laser light source and compares the setup data with the feedback signal to generate an adjust signal. The driver circuit receives the adjust signal and adjusts the drive current according to the adjust signal.
    Type: Application
    Filed: October 10, 2018
    Publication date: July 4, 2019
    Inventors: YU-CHENG SONG, CHIH-CHUN CHEN, FU-SHUN HO, CHIEN-HUNG LU
  • Publication number: 20190205357
    Abstract: A method for browsing virtual reality (VR) webpage content is provided. The browsing method includes: identifying a device information of a VR helmet by a native application; sending out a notification message by a first browser when it is detected that a VR webpage is browsed; retrieving a webpage information corresponding to the VR webpage and providing the webpage information to the native application by an extension component of the first browser in response to the notification message; determining, by the native application, whether the first browser supports the VR helmet to display a VR content of the VR webpage according to the device information; opening the VR webpage through a second browser, which supports the VR helmet to display the VR content, by the native application according to the webpage information when it is determined that the first browser does not support the VR helmet.
    Type: Application
    Filed: December 11, 2018
    Publication date: July 4, 2019
    Applicant: Acer Incorporated
    Inventors: Shih-Hao LIN, Chao-Kuang YANG, Wen-Cheng HSU, Chih-Sheng CHEN, Siang-Jyun CHENG
  • Publication number: 20190204730
    Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.
    Type: Application
    Filed: December 20, 2018
    Publication date: July 4, 2019
    Inventors: Yun-Yue LIN, Hsuan-Chen CHEN, Chih-Cheng LIN, Hsin-Chang LEE, Yao-Ching KU, Wei-Jen LO, Anthony YEN, Chin-Hsiang LIN, Mark CHIEN
  • Patent number: 10337983
    Abstract: The present disclosure generally relates to an optical measurement module, an optical measurement device, and a method for optical measurement. The optical measurement module provides optical architecture to measure the optical properties of an analyte. The optical measurement device comprising the optical measurement module is configured to measure the optical properties of an analyte. The method for the optical measurement provides steps for optical measurement.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: July 2, 2019
    Assignee: Taiwan Biophotonic Corporation
    Inventors: Yu-Tang Li, Chang-Sheng Chu, Pei-Cheng Ho, Kuan-Jui Ho, Shuang-Chao Chung, Chih-Hsun Fan, Jyh-Chern Chen
  • Publication number: 20190196224
    Abstract: A dual defocus lens is disclosed in the present invention. The dual defocus lens comprises a refractive-error correction part, a positioning part and a periphery part. The refractive-error correction part comprises a central optical region, a first defocus region and a second defocus region. The first defocus region, the second defocus region, the positioning part and the periphery part are all concentric to the central optical region having the same center as the refractive-error correction part. The first defocus region and the central optical region have different diopters individually for correcting the positions of imaging on the retina. The second defocus region having small radius of curvature provides shorter focus for imaging in the front of the retina. Thus, the retina will not be elongated or deformed gradually due to the image beyond the retina so that the myopia can be greatly controlled.
    Type: Application
    Filed: October 3, 2018
    Publication date: June 27, 2019
    Inventors: HSU-KUEI HSIAO, CHIH-CHENG CHEN, HSIEN-SHENG LIAO
  • Patent number: 10332991
    Abstract: Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other 3 sides of the first gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first gate electrode.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jr-Jung Lin, Chih-Han Lin, Jin-Aun Ng, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20190171198
    Abstract: A semiconductor manufacturing system includes an operating terminal, a first controller, and a plurality of second controllers. The operating terminal controls a main controller. Each of the plurality of second controllers is electrically connected to the first controller. In an initial or default state, the operating terminal controls the first controller as a main controller, and when the first controller fails, the operating terminal controls one of the plurality of the second controllers as a main controller, the others of the plurality of second controllers being controlled by the main controller.
    Type: Application
    Filed: May 28, 2018
    Publication date: June 6, 2019
    Inventors: YI-CHUN CHIU, CHUN-KAI HUANG, CHIH-CHENG LU, CHUN-CHUNG CHEN, CHEN-TSU FU, SHENG-FU TSAI
  • Patent number: 10310941
    Abstract: A data encoding method, a memory control circuit unit and a memory storage device are provided. The method includes: writing a first data into a first physical programming units; writing a second data into a second physical programming units; encoding by using the first data without using the second data to generate a first encoded data; encoding by using the second data and a first sub-data of the first data to generate a second encoded data; and writing the first encoded data and the second encoded data into a third physical programming unit and a fourth physical programming unit.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: June 4, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Chih-Kang Yeh, Yu-Cheng Hsu, Szu-Wei Chen
  • Patent number: 10312352
    Abstract: In some embodiments, a field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung Jung Chang
  • Patent number: 10312925
    Abstract: This invention discloses a multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (pipelined ADC). The MDAC includes an operational amplifier. The MDAC samples a differential input signal in a sampling phase and performs subtraction and multiplication operations in an amplification phase according to a first reference voltage and a second reference voltage. The common-mode voltage of the first reference voltage and the second reference voltage is not substantially equal to the common-mode voltage of the differential input signal; and/or the voltage difference between the first reference voltage and the second reference voltage is not substantially equal to one half of an allowed maximum peak-to-peak value of the differential input signal. One of the first reference voltage and the second reference voltage can be ground.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: June 4, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chih-Lung Chen, Ying-Cheng Wu, Shih-Hsiung Huang