Patents by Inventor Chih-Cheng Chou

Chih-Cheng Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190058255
    Abstract: An antenna device includes a circuit board and at least one chip antenna. The circuit board includes a clearance area and at least one signal feeding line disposed in the clearance area. The chip antenna includes a substrate and at least one resonance unit partially or wholly disposed on the surface of or within the substrate. The chip antenna is disposed in the clearance area of the circuit board and the resonance unit of the chip antenna is connected to the signal feeding line. A shortest distance from an edge of the clearance area to a nearest edge of the circuit board is greater than 1/10 of a smallest width of the circuit board. Therefore, the polarization direction of the chip antenna is approximately perpendicular to the upper surface of the circuit board, as well as the direction of the strongest signal strength of the radiation pattern is approximately parallel to the upper surface of the circuit board.
    Type: Application
    Filed: August 17, 2018
    Publication date: February 21, 2019
    Inventors: CHIH-SHEN CHOU, TSUNG-SHOU YEH, HSIANG-CHENG YANG, HUNG-YI CHANG
  • Publication number: 20190051609
    Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.
    Type: Application
    Filed: October 18, 2018
    Publication date: February 14, 2019
    Inventors: Wen-Sung HSU, Tao CHENG, Nan-Cheng CHEN, Che-Ya CHOU, Wen-Chou WU, Yen-Ju LU, Chih-Ming HUNG, Wei-Hsiu HSU
  • Publication number: 20190051559
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.
    Type: Application
    Filed: October 4, 2018
    Publication date: February 14, 2019
    Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih-Pei Chou, Chia-Chieh Lin
  • Patent number: 10078257
    Abstract: The invention discloses an oscillating lens module and a projector. The oscillating lens module includes a frame, a first coil, a lens, and a second coil. The first coil and the second coil are connected to the frame and located in a magnetic field, wherein the first coil and the second coil are adapted to be electrified and to oscillate about a first axis and a second axis respectively via the magnetic field. The lens is connected to the first coil, wherein the lens is adapted to oscillate along with the first coil. An oscillation phase of the second coil is opposite to an oscillation phase of the first coil, such that forces applied on the frame by the first coil and the second coil are counterbalanced, so as to prevent the oscillating lens module from over vibrating which makes projection images shake and makes noise.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: September 18, 2018
    Assignee: Coretronic Corporation
    Inventors: Shang-Hsuang Wu, Tsung-Ching Lin, Chih-Cheng Chou
  • Patent number: 10002602
    Abstract: A noise-reducing fan system, comprising a motor, a fan body, a plurality of magnetic-inducing elements, a magnetic field generator and a noise-reducing sound source device, is provided. Here, the fan body is mounted on the motor. The fan body comprises a plurality of blades, on which the plurality of magnetic-inducing elements are disposed, respectively. The magnetic field generator, which may generate a magnetic field, is employed for driving the plurality of magnetic-inducing elements to vibrate the plurality of blades and generate a vibration sound, so that at least one portion of the noise emitted from the fan body as rotating may be counterbalanced. The noise-reducing sound source device is disposed on a predetermined position and may send out a noise-reducing sound, so that the noise-reducing sound may counterbalance at least the other portion of the noise emitted from the fan body as rotating.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: June 19, 2018
    Assignee: CORETRONIC CORPORATION
    Inventors: Shang-Hsuang Wu, Chih-Cheng Chou
  • Publication number: 20180149533
    Abstract: The present invention provides an axial rotary type torque sensor comprising a planetary gear set disposed along a central axis between an input shaft and an output shaft. The input shaft drives the sun gear which meshes with planetary gears, and the planetary gears mesh with the ring gear of the planetary gear set to rotate along the circumference of the central axis. The ring gear is connected with a plurality of strip-like beams. At least one strain gauge is attached to the beams. One ending portion of the beam is fixed and the other ending portion is used for bearing a tangential force applied on the ring gear to generate a deformation at a rotation direction of a circumference. A strain gauge which senses the strain of the deformation used as a torque sensing value between the input shaft and the output shaft, thereby improving the poor sensing accuracy and sensitivity of the conventional torque sensors and solving the problem that the radial volume cannot be effectively reduced.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 31, 2018
    Inventors: YUEH-YANG HU, CHIH-CHENG CHOU, MENG-JEN CHIU
  • Patent number: 9846761
    Abstract: A layout of an integrated circuit design is provided and a plurality of multiple patterning decompositions is determined from the layout. Each decomposition of the plurality of multiple patterning decompositions includes patterns separated into masks. One or more files are generated that include sensitivities of pattern capacitances to changes in spacing between patterns due to mask shifts. Using the sensitivities and changes in spacing, respective worst-case performance values are determined for each decomposition. A mask set is selected based on the worst-case performance values.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: December 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Chou, Te-Yu Liu, Ke-Ying Su, Hsien-Hsin Sean Lee
  • Publication number: 20170243574
    Abstract: A noise-reducing fan system, comprising a motor, a fan body, a plurality of magnetic-inducing elements, a magnetic field generator and a noise-reducing sound source device, is provided. Here, the fan body is mounted on the motor. The fan body comprises a plurality of blades, on which the plurality of magnetic-inducing elements are disposed, respectively. The magnetic field generator, which may generate a magnetic field, is employed for driving the plurality of magnetic-inducing elements to vibrate the plurality of blades and generate a vibration sound, so that at least one portion of the noise emitted from the fan body as rotating may be counterbalanced. The noise-reducing sound source device is disposed on a predetermined position and may send out a noise-reducing sound, so that the noise-reducing sound may counterbalance at least the other portion of the noise emitted from the fan body as rotating.
    Type: Application
    Filed: December 7, 2016
    Publication date: August 24, 2017
    Inventors: SHANG-HSUANG WU, CHIH-CHENG CHOU
  • Patent number: 9575041
    Abstract: A gas cross-sensitivity analysis method is provided. The method includes, an injection frequency signal is generated from a first gas. A second gas sensing signal is captured from a second gas. Then, the second gas sensing signal is converted to a second gas sensing frequency signal by using Fast Fourier Transform. Further, a sensing peak frequency signal is determined from peak frequency of the second gas sensing frequency signal. The injection frequency signal and the sensing peak frequency signal are analyzed. A gas cross-sensitivity effect can be direct interpretation by a singular indication between the injection frequency signal and the sensing peak frequency signal.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: February 21, 2017
    Assignee: Automotive Research & Testing Center
    Inventors: Yong-Yuan Ku, Ya-Lun Chen, Chia-Jui Chiang, Yu-Hsuan Su, Chih-Cheng Chou
  • Publication number: 20170004252
    Abstract: A layout of an integrated circuit design is provided and a plurality of multiple patterning decompositions is determined from the layout. Each decomposition of the plurality of multiple patterning decompositions includes patterns separated into masks. One or more files are generated that include sensitivities of pattern capacitances to changes in spacing between patterns due to mask shifts. Using the sensitivities and changes in spacing, respective worst-case performance values are determined for each decomposition. A mask set is selected based on the worst-case performance values.
    Type: Application
    Filed: September 15, 2016
    Publication date: January 5, 2017
    Inventors: Chih-Cheng CHOU, Te-Yu LIU, Ke-Ying SU, Hsien-Hsin Sean LEE
  • Publication number: 20170003578
    Abstract: The invention discloses an oscillating lens module and a projector. The oscillating lens module includes a frame, a first coil, a lens, and a second coil. The first coil and the second coil are connected to the frame and located in a magnetic field, wherein the first coil and the second coil are adapted to be electrified and to oscillate about a first axis and a second axis respectively via the magnetic field. The lens is connected to the first coil, wherein the lens is adapted to oscillate along with the first coil. An oscillation phase of the second coil is opposite to an oscillation phase of the first coil, such that forces applied on the frame by the first coil and the second coil are counterbalanced, so as to prevent the oscillating lens module from over vibrating which makes projection images shake and makes noise.
    Type: Application
    Filed: April 21, 2016
    Publication date: January 5, 2017
    Inventors: Shang-Hsuang Wu, Tsung-Ching Lin, Chih-Cheng Chou
  • Patent number: 9471738
    Abstract: A method comprises processing a layout of an integrated circuit to determine one or more attributes of one or more components of the integrated circuit. The method also comprises extracting one or more process parameters from a process file associated with manufacturing the integrated circuit. The one or more process parameters are extracted from the process file based on a computation of one or more logic functions included in the process file. The computation is based on the one or more attributes. The method further comprises calculating a capacitance value between at least two components of the integrated circuit based on the one or more process parameters and a capacitance determination rule included in the process file. At least one of the one or more process parameters, the one or more logic functions, or the capacitance determination rule is editable based on a user input.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: October 18, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Chou, Tsung-Han Wu, Ke-ying Su, Hsien-Hsin Sean Lee, Chung-Hsing Wang
  • Patent number: 9448467
    Abstract: A system and method comprising providing a layout of an integrated circuit design, generating, by a processor, a plurality of multiple patterning decompositions from the layout, determining a maximum mask shift between the first mask and the second mask and simulating a worst-case performance value for each of the plurality of multiple patterning decompositions using one or more mask shifts within a range defined by the maximum mask shift. Further, each of the plurality of multiple patterning decompositions comprise patterns separated to a first mask and a second mask of a multiple patterning mask set.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Chou, Te-Yu Liu, Ke-Ying Su, Hsien-Hsin Sean Lee
  • Publication number: 20160232270
    Abstract: A method comprises processing a layout of an integrated circuit to determine one or more attributes of one or more components of the integrated circuit. The method also comprises extracting one or more process parameters from a process file associated with manufacturing the integrated circuit. The one or more process parameters are extracted from the process file based on a computation of one or more logic functions included in the process file. The computation is based on the one or more attributes. The method further comprises calculating a capacitance value between at least two components of the integrated circuit based on the one or more process parameters and a capacitance determination rule included in the process file. At least one of the one or more process parameters, the one or more logic functions, or the capacitance determination rule is editable based on a user input.
    Type: Application
    Filed: February 5, 2015
    Publication date: August 11, 2016
    Inventors: Chih-Cheng CHOU, Tsung-Han WU, Ke-Ying SU, Hsien-Hsin Sean LEE, Chung-Hsing WANG
  • Publication number: 20150276698
    Abstract: A gas cross-sensitivity analysis method is provided. The method includes, an injection frequency signal is generated from a first gas. A second gas sensing signal is captured from a second gas. Then, the second gas sensing signal is converted to a second gas sensing frequency signal by using Fast Fourier Transform. Further, a sensing peak frequency signal is determined from peak frequency of the second gas sensing frequency signal. The injection frequency signal and the sensing peak frequency signal are analyzed. A gas cross-sensitivity effect can be direct interpretation by a singular indication between the injection frequency signal and the sensing peak frequency signal.
    Type: Application
    Filed: July 18, 2014
    Publication date: October 1, 2015
    Inventors: Yong-Yuan KU, Ya-Lun CHEN, Chia-Jui CHIANG, Yu-Hsuan SU, Chih-Cheng CHOU
  • Publication number: 20150234975
    Abstract: A system and method comprising providing a layout of an integrated circuit design, generating, by a processor, a plurality of multiple patterning decompositions from the layout, determining a maximum mask shift between the first mask and the second mask and simulating a worst-case performance value for each of the plurality of multiple patterning decompositions using one or more mask shifts within a range defined by the maximum mask shift. Further, each of the plurality of multiple patterning decompositions comprise patterns separated to a first mask and a second mask of a multiple patterning mask set.
    Type: Application
    Filed: February 18, 2014
    Publication date: August 20, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMAPNY, LTD.
    Inventors: Chih-Cheng CHOU, Te-Yu LIU, Ke-Ying SU, Hsien-Hsin Sean LEE
  • Patent number: 8899911
    Abstract: The invention provides a heat-dissipating system and a control method thereof. The heat-dissipating system has a plurality of fans and is configured for adjusting rotation-speeds of the fans. The control method includes following steps: obtaining a plurality of rotation-speed values of the fans; computing out a rotation-speed reference value according to the rotation-speed values; when the rotation-speed reference value is greater than a first threshold value, decreasing the rotation-speeds of the fans through a corresponding fan control signal; when the rotation-speed reference value is less than a second threshold value, increasing the rotation-speeds of the fans through the corresponding fan control signal.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: December 2, 2014
    Assignee: Coretronic Corporation
    Inventors: Chih-Cheng Chou, Wen-Hsien Su, Tsung-Ching Lin, Chao-Nan Chien
  • Patent number: 8745559
    Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die including at least one metal layer to be formed using at least one of a single patterning process or a multi-patterning process, creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the metal layer of at least one die based on the technology file, simulating a performance of the integrated circuit based on the netlist, adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and repeating the simulating and adjusting to optimize the at least one of the capacitive or inductive couplings.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Cheng Chou, Ke-Ying Su
  • Publication number: 20130305196
    Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die including at least one metal layer to be formed using at least one of a single patterning process or a multi-patterning process, creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the metal layer of at least one die based on the technology file, simulating a performance of the integrated circuit based on the netlist, adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and repeating the simulating and adjusting to optimize the at least one of the capacitive or inductive couplings.
    Type: Application
    Filed: April 29, 2013
    Publication date: November 14, 2013
    Inventors: Chih-Cheng CHOU, Ke-Ying SU
  • Publication number: 20130101389
    Abstract: The invention provides a heat-dissipating system and a control method thereof. The heat-dissipating system has a plurality of fans and is configured for adjusting rotation-speeds of the fans. The control method includes following steps: obtaining a plurality of rotation-speed values of the fans; computing out a rotation-speed reference value according to the rotation-speed values; when the rotation-speed reference value is greater than a first threshold value, decreasing the rotation-speeds of the fans through a corresponding fan control signal; when the rotation-speed reference value is less than a second threshold value, increasing the rotation-speeds of the fans through the corresponding fan control signal.
    Type: Application
    Filed: July 16, 2012
    Publication date: April 25, 2013
    Applicant: CORETRONIC CORPORATION
    Inventors: Chih-Cheng Chou, Wen-Hsien Su, Tsung-Ching Lin, Chao-Nan Chien