Patents by Inventor Chih-Cheng Fu
Chih-Cheng Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11908516Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.Type: GrantFiled: August 27, 2021Date of Patent: February 20, 2024Assignee: Winbond Electronics Corp.Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
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Patent number: 11620500Abstract: A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.Type: GrantFiled: January 11, 2018Date of Patent: April 4, 2023Assignee: WINBOND ELECTRONICS CORP.Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao, Chih-Cheng Fu, Ming-Che Lin, Yu-Ting Chen, Seow-Fong (Dennis) Lim
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Publication number: 20220068382Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.Type: ApplicationFiled: August 27, 2021Publication date: March 3, 2022Applicant: Winbond Electronics Corp.Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
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Patent number: 11107983Abstract: A RRAM array and its manufacturing method are provided. The RRAM array includes a substrate having an array region which has a first region and a second region. The RRAM array includes a bottom electrode layer on the substrate, an oxygen ion reservoir layer on the bottom electrode layer, a diffusion barrier layer on the oxygen ion reservoir layer, a resistance switching layer on the diffusion barrier layer, and a top electrode layer on the resistance switching layer. The diffusion barrier layer in the first region is different from the diffusion barrier layer in the second region.Type: GrantFiled: October 1, 2020Date of Patent: August 31, 2021Assignee: WINBOND ELECTRONICS CORP.Inventors: Chih-Cheng Fu, Ming-Che Lin
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Patent number: 11024802Abstract: Provided is a method of fabricating a resistive memory including forming a first electrode and a second electrode opposite to each other; forming a variable resistance layer between the first electrode and the second electrode; forming an oxygen exchange layer between the variable resistance layer and the second electrode; and forming a protection layer at least covering sidewalls of the oxygen exchange layer.Type: GrantFiled: November 14, 2019Date of Patent: June 1, 2021Assignee: Winbond Electronics Corp.Inventors: Po-Yen Hsu, Ting-Ying Shen, Chia-Hua Ho, Chih-Cheng Fu, Frederick Chen
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Publication number: 20210104666Abstract: A RRAM array and its manufacturing method are provided. The RRAM array includes a substrate having an array region which has a first region and a second region. The RRAM array includes a bottom electrode layer on the substrate, an oxygen ion reservoir layer on the bottom electrode layer, a diffusion barrier layer on the oxygen ion reservoir layer, a resistance switching layer on the diffusion barrier layer, and a top electrode layer on the resistance switching layer. The diffusion barrier layer in the first region is different from the diffusion barrier layer in the second region.Type: ApplicationFiled: October 1, 2020Publication date: April 8, 2021Inventors: Chih-Cheng FU, Ming-Che LIN
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Patent number: 10770167Abstract: A memory storage apparatus and a forming method of a resistive memory device thereof are provided. A test forming voltage is applied to a redundant resistive memory device and a corresponding test current is read. A forming voltage applied to a main memory cell block is determined according to the test forming voltage, the test current, a forming current-voltage characteristic data and a target forming current.Type: GrantFiled: February 20, 2019Date of Patent: September 8, 2020Assignee: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Ming-Che Lin, Chien-Min Wu, He-Hsuan Chao, Chih-Cheng Fu, Shao-Ching Liao
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Publication number: 20200265914Abstract: A memory storage apparatus and a forming method of a resistive memory device thereof are provided. A test forming voltage is applied to a redundant resistive memory device and a corresponding test current is read. A forming voltage applied to a main memory cell block is determined according to the test forming voltage, the test current, a forming current-voltage characteristic data and a target forming current.Type: ApplicationFiled: February 20, 2019Publication date: August 20, 2020Applicant: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Ming-Che Lin, Chien-Min Wu, He-Hsuan Chao, Chih-Cheng Fu, Shao-Ching Liao
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Patent number: 10636484Abstract: A memory device including a plurality of memory units; at least one geometric mean operator coupled to at least two of the plurality of memory units; and a memory state reader coupled to the at least one geometric mean operator to read a memory state of the plurality of memory units.Type: GrantFiled: September 12, 2018Date of Patent: April 28, 2020Assignee: Winbond Electronics CorporationInventors: Frederick Chen, Ping-Kun Wang, Chih-Cheng Fu, Chien-Min Wu
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Publication number: 20200082879Abstract: A memory device including a plurality of memory units; at least one geometric mean operator coupled to at least two of the plurality of memory units; and a memory state reader coupled to the at least one geometric mean operator to read a memory state of the plurality of memory units.Type: ApplicationFiled: September 12, 2018Publication date: March 12, 2020Inventors: Frederick CHEN, Ping-Kun WANG, Chih-Cheng FU, Chien-Min WU
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Publication number: 20200083446Abstract: Provided is a method of fabricating a resistive memory including forming a first electrode and a second electrode opposite to each other; forming a variable resistance layer between the first electrode and the second electrode; forming an oxygen exchange layer between the variable resistance layer and the second electrode; and forming a protection layer at least covering sidewalls of the oxygen exchange layer.Type: ApplicationFiled: November 14, 2019Publication date: March 12, 2020Applicant: Winbond Electronics Corp.Inventors: Po-Yen Hsu, Ting-Ying Shen, Chia-Hua Ho, Chih-Cheng Fu, Frederick Chen
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Patent number: 10522755Abstract: Provided are a resistive memory and a method of fabricating the resistive memory. The resistive memory includes a first electrode, a second electrode, a variable resistance layer, an oxygen exchange layer, and a protection layer. The first electrode and the second electrode are arranged opposite to each other. The variable resistance layer is arranged between the first electrode and the second electrode. The oxygen exchange layer is arranged between the variable resistance layer and the second electrode. The protection layer is arranged at least on sidewalls of the oxygen exchange layer.Type: GrantFiled: March 9, 2016Date of Patent: December 31, 2019Assignee: Winbond Electronics Corp.Inventors: Po-Yen Hsu, Ting-Ying Shen, Chia-Hua Ho, Chih-Cheng Fu, Frederick Chen
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Patent number: 10490739Abstract: A method of forming a one-time-programmable resistive random access memory bit includes forming a resistive switching layer on a bottom electrode layer. The method also includes forming a top electrode layer on the resistive switching layer. The method also includes applying a forming voltage to the resistive switching layer, such that the electric potential of the top electrode layer is lower than that of the bottom electrode layer. The method also includes performing a bake process on the resistive switching layer. The vacancies in the resistive switching layer are randomly distributed.Type: GrantFiled: January 10, 2018Date of Patent: November 26, 2019Assignee: Winbond Electronics Corp.Inventors: Frederick Chen, Ping-Kun Wang, Chih-Cheng Fu, Chien-Min Wu, Shao-Ching Liao
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Publication number: 20190214556Abstract: A method of forming a one-time-programmable resistive random access memory bit includes forming a resistive switching layer on a bottom electrode layer. The method also includes forming a top electrode layer on the resistive switching layer. The method also includes applying a forming voltage to the resistive switching layer, such that the electric potential of the top electrode layer is lower than that of the bottom electrode layer. The method also includes performing a bake process on the resistive switching layer. The vacancies in the resistive switching layer are randomly distributed.Type: ApplicationFiled: January 10, 2018Publication date: July 11, 2019Inventors: Frederick CHEN, Ping-Kun WANG, Chih-Cheng FU, Chien-Min WU, Shao-Ching LIAO
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Publication number: 20190213468Abstract: A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.Type: ApplicationFiled: January 11, 2018Publication date: July 11, 2019Inventors: Frederick CHEN, Ping-Kun WANG, Shao-Ching LIAO, Chih-Cheng FU, Ming-Che LIN, Yu-Ting CHEN, Seow-Fong (Dennis) LIM
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Patent number: 10340450Abstract: A resistive random access memory (RRAM) structure and its forming method are provided, which includes an interlayer dielectric layer on a substrate. The interlayer dielectric layer is a dielectrics including oxygen. The RRAM structure also includes an oxygen-diffusion barrier layer on the interlayer dielectric layer, and a bottom electrode layer on the oxygen-diffusion barrier layer. The bottom electrode layer includes a first electrode layer, a first oxygen-rich layer on the first electrode layer, and a second electrode layer on the first oxygen-rich layer. The RRAM structure also includes a resistance switching layer on the bottom electrode layer, and a top electrode layer on the resistance switching layer.Type: GrantFiled: July 26, 2017Date of Patent: July 2, 2019Assignee: WINBOND ELECTRONICS CORP.Inventors: Po-Yen Hsu, Chih-Cheng Fu, Ting-Ying Shen
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Publication number: 20180269389Abstract: A resistive random access memory (RRAM) structure and its forming method are provided, which includes an interlayer dielectric layer on a substrate. The interlayer dielectric layer is a dielectrics including oxygen. The RRAM structure also includes an oxygen-diffusion barrier layer on the interlayer dielectric layer, and a bottom electrode layer on the oxygen-diffusion barrier layer. The bottom electrode layer includes a first electrode layer, a first oxygen-rich layer on the first electrode layer, and a second electrode layer on the first oxygen-rich layer. The RRAM structure also includes a resistance switching layer on the bottom electrode layer, and a top electrode layer on the resistance switching layer.Type: ApplicationFiled: July 26, 2017Publication date: September 20, 2018Inventors: Po-Yen HSU, Chih-Cheng FU, Ting-Ying SHEN
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Publication number: 20170125673Abstract: Provided are a resistive memory and a method of fabricating the resistive memory. The resistive memory includes a first electrode, a second electrode, a variable resistance layer, an oxygen exchange layer, and a protection layer. The first electrode and the second electrode are arranged opposite to each other. The variable resistance layer is arranged between the first electrode and the second electrode. The oxygen exchange layer is arranged between the variable resistance layer and the second electrode. The protection layer is arranged at least on sidewalls of the oxygen exchange layer.Type: ApplicationFiled: March 9, 2016Publication date: May 4, 2017Inventors: Po-Yen Hsu, Ting-Ying Shen, Chia-Hua Ho, Chih-Cheng Fu, Frederick Chen
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Patent number: 8237752Abstract: A color calibrator of a display apparatus is disclosed. The color calibrator includes a color estimator for receiving a plurality of digital counts of initial colors of an image signal. The color estimator includes a first operator, a gray value electrical-optical converter, a mixed-color electrical-optical converter, an initial color electrical-optical converter, a plurality of linear transformers and a weighting operator. The gray value electrical-optical converter, the mixed-color electrical-optical converter and the initial color electrical-optical converter convert a gray value digital count, a mixed color digital count and an initial color digital count for generating a plurality conversion outputs according to a plurality of gray conversion curves, a plurality of mixed color conversion curves and a plurality of initial color converting curve. The weighting operator receives the conversion outputs and a plurality of weighting values to generate an analysis output signal.Type: GrantFiled: March 11, 2010Date of Patent: August 7, 2012Assignee: Chunghwa Picture Tubes, Ltd.Inventors: Chun-Hsien Chou, Ray-Chin Wu, Chih-Cheng Fu, Cheng-Chieh Wu, Shing-Shi Tseng, Chia-Ming Huang
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Publication number: 20110122160Abstract: A color calibrator of a display apparatus is disclosed. The color calibrator includes a color estimator for receiving a plurality of digital counts of initial colors of an image signal. The color estimator includes a first operator, a gray value electrical-optical converter, a mixed-color electrical-optical converter, an initial color electrical-optical converter, a plurality of linear transformers and a weighting operator. The gray value electrical-optical converter, the mixed-color electrical-optical converter and the initial color electrical-optical converter convert a gray value digital count, a mixed color digital count and an initial color digital count for generating a plurality conversion outputs according to a plurality of gray conversion curves, a plurality of mixed color conversion curves and a plurality of initial color converting curve. The weighting operator receives the conversion outputs and a plurality of weighting values to generate an analysis output signal.Type: ApplicationFiled: March 11, 2010Publication date: May 26, 2011Applicant: CHUNGHWA PICTURE TUBES, LTD.Inventors: Chun-Hsien Chou, Ray-Chin Wu, Chih-Cheng Fu, Cheng-Chieh Wu, Shing-Shi Tseng, Chia-Ming Huang