Abstract: A method for calculating an error of a sampling clock is provided. The sampling clock is used for sampling a signal to generate a first sample data group and a second sample data group. Each of the first and second sample data groups includes a header having a predetermined sequence. The method includes: performing a correlation operation on the first and second sample data groups with data of the predetermined format to obtain first and second correlation results, respectively; comparing the first and second correlation results to generate a sample data group offset; and generating the error of the sampling clock according to the sample data group offset and a time difference between the first and second sample data groups.

Abstract: A correcting apparatus for timing recovery of a receiver is provided. The receiver includes a timing recovery module that outputs a first symbol and a second symbol. The correcting apparatus includes: a channel impulse response module, configured to generate a first set of peak times and a second set of peak times according to the first symbol and the second symbol, respectively; and a calculation module, configured to calculate a correction signal according to a relationship between the first and second sets of peak times and to send the correction signal to the timing recovery module.

Abstract: A receiving apparatus applied to a receiving end of a communication device having an equalizer is provided. The receiving apparatus includes a filter and a channel estimator. The filter filters a received signal to reduce a multipath effect of the received signal and outputs a filtered signal. The channel estimator performs channel estimation on the received signal to generate an estimation result. The estimation result is for determining which of the received signal and the filtered signal is to be selected and sent to the equalizer.

Abstract: A method for calculating an error of a sampling clock is provided. The sampling clock is used for sampling a signal to generate a first sample data group and a second sample data group. Each of the first and second sample data groups includes a header having a predetermined sequence. The method includes: performing a correlation operation on the first and second sample data groups with data of the predetermined format to obtain first and second correlation results, respectively; comparing the first and second correlation results to generate a sample data group offset; and generating the error of the sampling clock according to the sample data group offset and a time difference between the first and second sample data groups.

Abstract: A timing recovery apparatus for compensating a sampling frequency offset of an input signal is provided. The timing recovery apparatus includes a timing error corrector configured to generate an output signal according to the input signal and a calibration signal, a gain controller configured to adjust at least one of a signal edge low-frequency error component and a signal edge high-frequency error component of the output signal and accordingly generate an adjusted signal, a timing error detector configured to generate an error signal according to the adjusted signal, and a calibration signal generator coupled to the timing error detector and the timing error corrector, for generating the calibration signal according to the error signal and outputting the calibration signal to the timing error corrector to compensate the sampling frequency offset of the input signal.

Abstract: A correcting apparatus for timing recovery of a receiver is provided. The receiver includes a timing recovery module that outputs a first symbol and a second symbol. The correcting apparatus includes: a channel impulse response module, configured to generate a first set of peak times and a second set of peak times according to the first symbol and the second symbol, respectively; and a calculation module, configured to calculate a correction signal according to a relationship between the first and second sets of peak times and to send the correction signal to the timing recovery module.

Abstract: A receiving apparatus applied to a receiving end of a communication device having an equalizer is provided. The receiving apparatus includes a filter and a channel estimator. The filter filters a received signal to reduce a multipath effect of the received signal and outputs a filtered signal. The channel estimator performs channel estimation on the received signal to generate an estimation result. The estimation result is for determining which of the received signal and the filtered signal is to be selected and sent to the equalizer.

Abstract: A timing recovery apparatus for compensating a sampling frequency offset of an input signal is provided. The timing recovery apparatus includes a timing error corrector configured to generate an output signal according to the input signal and a calibration signal, a gain controller configured to adjust at least one of a signal edge low-frequency error component and a signal edge high-frequency error component of the output signal and accordingly generate an adjusted signal, a timing error detector configured to generate an error signal according to the adjusted signal, and a calibration signal generator coupled to the timing error detector and the timing error corrector, for generating the calibration signal according to the error signal and outputting the calibration signal to the timing error corrector to compensate the sampling frequency offset of the input signal.

Abstract: A signal detecting method and a receiver using the same are provided. The method includes the following steps. A receiving signal vector y is received through a number of channels, wherein the receiving signal vector y corresponds to a transmitting signal vector x transmitted by at least one of the channels. A channel matrix H is determined, wherein the channel matrix H represents at least one of the channels. A factorization matrix D is chosen, wherein D is invertible to make the channel matrix H expressed as H={tilde over (H)}D, and {tilde over (H)} is a corresponding channel matrix. The factorization matrix D is determined to make an expected value of the signal estimate error become smaller. The receiving signal vector y is detected to estimate the transmitting signal vector x according to the corresponding channel matrix {tilde over (H)} and the factorization matrix D.

Abstract: An electrical connector assembly has a socket, a plug, a sliding slot, and a fastener. The socket includes having a slot and a first latch disposed at one side of the slot. The plug is insertable into the slot of the socket, and is provided with a second latch corresponding to the first latch of the socket. The sliding slot is disposed on the second latch corresponding to the first latch of the socket. The fastener is positioned on the second latch of the plug. When the plug is inserted into the socket, the fastener can be moved to connect the first and second latches to fasten together the plug and socket. Furthermore, the fastener can be moved along the sliding slot in a direction away from the first latch to unfasten the plug and the socket.

Abstract: Alarm control circuitry is provided for a Universal Serial Bus (USB) port connectible device including an alarm generator emitting an audible alarm when powered by internal voltage from a capacitor charged by external voltage from a computer during connection of the device to a computer and actuated with a power off detection circuit in the condition that termination of power from the computer to the device is detected. Provision for an optional base unit with passive RFID in the alarm control circuitry includes an RF transceiver, ID reader, timer and counter causing alarm activation if a ‘reflected’ RF signal is not received in a certain amount of time. An exemplary power off detection circuit outputs an alarm control signal digital logic ‘1’ in alarm generator actuation using an AND gate fed by internal voltage and external voltage reverse logic.

Abstract: An electrical connector assembly has a socket, a plug, a sliding slot, and a fastener. The socket includes having a slot and a first latch disposed at one side of the slot. The plug is insertable into the slot of the socket, and is provided with a second latch corresponding to the first latch of the socket. The sliding slot is disposed on the second latch corresponding to the first latch of the socket. The fastener is positioned on the second latch of the plug. When the plug is inserted into the socket, the fastener can be moved to connect the first and second latches to fasten together the plug and socket. Furthermore, the fastener can be moved along the sliding slot in a direction away from the first latch to unfasten the plug and the socket.

Abstract: An electrical connector having a socket, a latch rod, a plug, and a pulling mechanism. The socket includes a slot, with the latch rod connecting to the socket. The plug includes a lock on each of opposite side walls, with the plug insertable into the slot. The latch rod is rotatable and receivable in the lock. The pulling mechanism is located on the plug, with the latch rod being pressable on the pulling mechanism to secure it. The pulling mechanism enables the latch rod to be easily released from the lock.

Abstract: Reminding of the owner of a Universal Serial Bus (USB) port connectible device that the same has been left connected to a USB port of a powered computer is provided by an alarm disposed on a portable base for the device activated by cessation of reception of a limited range radio frequency (RF) signal. Transmission is powered by the computer through the USB port. The portable base has an independent power source for reception/alarm circuitry preferably switched on by separation of a USB port connectible device and/or signalling attachment from the portable base and switched off by physical reunion of the same. Alarm activation while retrieving the USB port connectible device from the USB port of a computer is avoided with an alarm activation delay exceeding in duration a transmission interval minimizing the likelihood of RF signal interference between multiple proximate reminders or other signals of the same RF.

Abstract: A signal detecting method and a receiver using the same are provided. The method includes the following steps. A receiving signal vector y is received through a number of channels, wherein the receiving signal vector y corresponds to a transmitting signal vector x transmitted by at least one of the channels. A channel matrix H is determined, wherein the channel matrix H represents at least one of the channels. A factorization matrix D is chosen, wherein D is invertible to make the channel matrix H expressed as H={tilde over (H)}D, and {tilde over (H)} is a corresponding channel matrix. The factorization matrix D is determined to make an expected value of the signal estimate error become smaller. The receiving signal vector y is detected to estimate the transmitting signal vector x according to the corresponding channel matrix {tilde over (H)} and the factorization matrix D.

Abstract: Multiple applications upon an IC microprocessor are protected with bi-modal CPU operation, either application or system mode, using an operation flag determining the mode and dependent upon a mode change interrupt which clears all working memory unnecessary to operation in the next mode. Access authorization setting program and data memory boundaries according to the particular custom command in comparison registers is utilized in application initialization. From application mode, data files are accessed only through a system subroutine. Request of an address beyond the territory assigned to the custom command utilized results in a hardware interrupt which clears all working memory and registers unnecessary to forward a status word indicating abnormal termination. Application completion forwards the result with a status word indicating successful completion.

Abstract: Multiple applications upon an IC microprocessor are protected with bi-modal CPU operation, either in application mode or system mode, using an operation flag determining the mode and a functional interrupt with each mode change. Direct subroutine calling is replaced by a software interrupt which clears all working memory and registers except those holding parameters including the return address placed in stack. Access authorization utilizing a comparison register containing application and system memory boundaries according to the particular custom command utilized is associated with a mode change interrupt in application initialization. System subroutine running involves two mode change interrupts, from application to system and back, and includes access authorization.