Patents by Inventor Chih-Cheng Liang

Chih-Cheng Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240114614
    Abstract: Disclosed is a thermal conduction-electrical conduction isolated circuit board with a ceramic substrate and a power transistor embedded, mainly comprising: a dielectric material layer, a heat-dissipating ceramic block, a securing portion, a stepped metal electrode layer, a power transistor, and a dielectric material packaging, wherein a via hole is formed in the dielectric material layer, the heat-dissipating ceramic block is correspondingly embedded in the via hole, the heat-dissipating ceramic block has a thermal conductivity higher than that of the dielectric material layer and a thickness less than that of the dielectric material layer, the stepped metal electrode layer conducts electricity and heat for the power transistor, the dielectric material packaging is configured to partially expose the source connecting pin, drain connecting pin, and gate connecting pin of the encapsulated stepped metal electrode layer.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: HO-CHIEH YU, CHEN-CHENG-LUNG LIAO, CHUN-YU LIN, JASON AN CHENG HUANG, CHIH-CHUAN LIANG, KUN-TZU CHEN, NAI-HIS HU, LIANG-YO CHEN
  • Publication number: 20170329684
    Abstract: A method for performing data recovery in a redundant storage system and an associated apparatus are provided. The method includes: determining a state of a cache block of a plurality of cache blocks, in which the plurality of storage devices includes a set of Hard Disk Drives (HDDs) and a set of Solid State Drives (SSDs), an SSD Redundant Array of Independent Disk (RAID) of the redundant storage system includes the set of SSDs, and an HDD RAID of the redundant storage system includes the set of HDDs, in which the SSD RAID is utilized as a cache system of the HDD RAID and includes the plurality of cache blocks; and performing a retry-read operation on at least one of the HDD RAID and the SSD RAID according to the state of the cache block, to obtain a correct version of data within the redundant storage system.
    Type: Application
    Filed: April 20, 2017
    Publication date: November 16, 2017
    Inventors: Huai-En Lien, Chung-Chiang Cheng, Chien-Kuan Yeh, Chih-Cheng Liang, Tzu-Lin Chang, Ning-Yen Chien, Hsuan-Ting Chen
  • Publication number: 20160371192
    Abstract: A method for performing cache management for a storage system and an associated apparatus are provided, where the storage system includes a plurality of storage devices. The method includes: utilizing a storage device of the plurality of storage devices as a cache of another storage device of the plurality of storage devices, in which an access speed of the storage device is higher than that of the other storage device, and the cache includes a plurality of cache blocks; and when a read miss of the cache occurs, reading data corresponding to at least one cache block from the other storage device to store the data into the cache, in which a data amount corresponding to the read miss is less than a data amount of each cache block of the plurality of cache blocks.
    Type: Application
    Filed: May 16, 2016
    Publication date: December 22, 2016
    Inventors: Yi-Chun Lin, Chih-Cheng Liang, Yu-Ting Wang, Hsuan-Ting Chen
  • Patent number: 8905773
    Abstract: A memory socket with a special contact mechanism comprising a plurality of socket pins arranged in two opposite rows leaning respectively against two inner projecting portions in a socket frame, and an interacting member movably installed between the two rows of the socket pins having a cam portion to pushes the socket pin at both sides away from the interacting member during the insertion of a memory module, so that the socket pin may be bended to contact the inserted memory module.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: December 9, 2014
    Assignee: Nanya Technology Corp.
    Inventor: Chih-Cheng Liang
  • Publication number: 20140235107
    Abstract: A memory socket with a special contact mechanism comprising a plurality of socket pins arranged in two opposite rows leaning respectively against two inner projecting portions in a socket frame, and an interacting member movably installed between the two rows of the socket pins having a cam portion to pushes the socket pin at both sides away from the interacting member during the insertion of a memory module, so that the socket pin may be bended to contact he inserted memory module.
    Type: Application
    Filed: February 20, 2013
    Publication date: August 21, 2014
    Applicant: NANYA TECHNOLOGY CORP.
    Inventor: Chih-Cheng Liang