Patents by Inventor Chih-Cheng Wu
Chih-Cheng Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240146085Abstract: The present disclosure provides a battery charging system and method. The battery charging method includes: determining a degree of healthy of a battery module according to an evaluation mechanism; setting a charging standard according to the degree of healthy; by handshaking with a charger, setting a charging voltage for the charger according to the charging standard to charge the battery module; and by the charger, perform a charging operation on the battery module until a fully charged condition is satisfied.Type: ApplicationFiled: October 31, 2023Publication date: May 2, 2024Inventors: Tsung-Nan WU, Chih-Hsiang HSU, Wei-Cheng CHEN
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Patent number: 11967596Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.Type: GrantFiled: August 5, 2021Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Guo-Huei Wu, Shih-Wei Peng, Wei-Cheng Lin, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien, Lee-Chung Lu
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Patent number: 11965217Abstract: A method and a kit for detecting Mycobacterium tuberculosis are provided. The method includes a step of performing a nested qPCR assay to a specimen. The nested qPCR assay includes a first round of amplification using external primers and a second round of amplification using internal primers and a probe. The external primers have sequences of SEQ ID NOs. 1 and 2, and the internal primers and the probe have sequences of SEQ ID NOs. 3 to 5.Type: GrantFiled: May 24, 2021Date of Patent: April 23, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Yi-Chen Li, Chih-Cheng Tsou, Min-Hsien Wu, Hsin-Yao Wang, Chien-Ru Lin
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Patent number: 11967272Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.Type: GrantFiled: December 9, 2022Date of Patent: April 23, 2024Assignees: AUO Corporation, National Cheng-Kung UniversityInventors: Chih-Lung Lin, Yi-Chen Huang, Chih-I Liu, Po-Cheng Lai, Ming-Yang Deng, Chia-En Wu, Ming-Hung Chuang, Chia-Tien Peng
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Publication number: 20240122669Abstract: An ear canal clamp for small animals includes a base and a clamping mechanism. The clamping mechanism includes two clamping arms movably mounted on the base, a biasing member mounted on the base and constrained between the clamping arms, and two ear canal positioning members mounted respectively to the clamping arms and facing each other. The clamping arms are configured to move toward each other and compress the biasing member to increase the distance between the ear canal positioning members. A biasing force generated by the biasing member when compressed is used to push the clamping arms to move oppositely with respect to each other.Type: ApplicationFiled: January 11, 2023Publication date: April 18, 2024Inventors: Chih-Wei PENG, Chun-Wei WU, Chun-Ying CAI, Yen CHENG
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Publication number: 20240128211Abstract: Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.Type: ApplicationFiled: April 27, 2023Publication date: April 18, 2024Inventors: Chih-Wei WU, An-Jhih SU, Hua-Wei TSENG, Ying-Ching SHIH, Wen-Chih CHIOU, Chun-Wei CHEN, Ming Shih YEH, Wei-Cheng WU, Der-Chyang YEH
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Patent number: 11961892Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: GrantFiled: June 10, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Patent number: 11955459Abstract: A package structure is provided. The package structure includes a first die and a second die, a dielectric layer, a bridge, an encapsulant, and a redistribution layer structure. The dielectric layer is disposed on the first die and the second die. The bridge is electrically connected to the first die and the second die, wherein the dielectric layer is spaced apart from the bridge. The encapsulant is disposed on the dielectric layer and laterally encapsulating the bridge. The redistribution layer structure is disposed over the encapsulant and the bridge. A top surface of the bridge is in contact with the RDL structure.Type: GrantFiled: March 7, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Hang Liao, Chih-Wei Wu, Jing-Cheng Lin, Szu-Wei Lu, Ying-Ching Shih
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Patent number: 11942652Abstract: The disclosure provides a limit device and a robot using the same. The limit device comprises a first connecting member, a transmission rod and a second connecting member. The first connecting member comprising a first main body portion and two first connecting elements. The two first connecting elements are arranged at intervals. The two first connecting elements are respectively connected to the first main body. The transmission rod comprising a first end and a second end. The first end and the second end are arranged at intervals. The first end penetrates through one of the two first connecting elements. The second end penetrates through the other one of the two first connecting element. The second connecting member provided with two indexing buckles. The two indexing buckles are arranged at intervals, each of the indexing buckles comprises a first limiting groove and a second limiting groove.Type: GrantFiled: April 13, 2022Date of Patent: March 26, 2024Assignees: Futaijing Precision Electronics (Yantai) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Chen-Ting Kao, Chi-Cheng Wen, Yu-Sheng Chang, Chih-Cheng Lee, Chiung-Hsiang Wu, Sheng-Li Yen, Yu-Cheng Zhang, Chang-Ju Hsieh, Chen Chao
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Publication number: 20240084455Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.Type: ApplicationFiled: February 8, 2023Publication date: March 14, 2024Inventors: Che Wei YANG, Chih Cheng SHIH, Kuo Liang LU, Yu JIANG, Sheng-Chan LI, Kuo-Ming WU, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
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Publication number: 20240088307Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
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Publication number: 20240088145Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.Type: ApplicationFiled: November 27, 2023Publication date: March 14, 2024Inventors: Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu, Chih-Hao Wang, Kuo-Cheng Ching
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Patent number: 11929417Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: GrantFiled: June 30, 2022Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Patent number: 11929318Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.Type: GrantFiled: May 10, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
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Publication number: 20160174837Abstract: A method for measuring two pupils includes a number of steps. A first visible light beam and a first invisible light beam are emitted toward a right eye. A second visible light beam and a second invisible light beam are emitted toward a left eye. The light beams reflected from the right eye and the left eye are received by an optical unit, and the first invisible light beam and the second invisible light beam are guided to an imaging unit by the optical unit. Images of the right eye and the left eye are respectively recorded through the first invisible light and the second invisible light beam propagated from the optical unit.Type: ApplicationFiled: April 14, 2015Publication date: June 23, 2016Inventors: Mang OU-YANG, Ting-Wei HUANG, Jin-Chern CHIOU, Mei-Lan KO, Bak-Sau YIP, Chih-Cheng WU, Wei-De JENG, Yin-Yuan CHEN, Bi-Shou SONE
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Patent number: 7730607Abstract: An apparatus for assembling cable to connector includes a jig holder and a cable jig. The jig holder has a basic board defining a mounting space capable of locating a connector in the front thereof. The cable jig located in the rear of the mounting space of the jig holder has an upper jig member and a lower jig member disposed beneath the upper jig member. One of the jig members protrudes to form first spaced-apart barriers. A first receiving passage is defined between each pair of adjacent first spaced-apart barriers. The other jig member defines second receiving passages for receiving the first spaced-apart barriers respectively. A second spaced-apart barrier is defined between every two adjacent second receiving passages to space the two adjacent second receiving passages apart. The second spaced-apart barriers are inserted in the first receiving passages respectively.Type: GrantFiled: November 6, 2007Date of Patent: June 8, 2010Assignee: Cheng Uei Precision Industry Co., Ltd.Inventors: Ming-Chia Chi, Chih-Cheng Wu, Yu-Tso Liu, Chin-Chiang Li, Yu-Hua Hsieh
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Publication number: 20090113699Abstract: An apparatus for assembling cable to connector includes a jig holder and a cable jig. The jig holder has a basic board defining a mounting space capable of locating a connector in the front thereof. The cable jig located in the rear of the mounting space of the jig holder has an upper jig member and a lower jig member disposed beneath the upper jig member. One of the jig members protrudes to form first spaced-apart barriers. A first receiving passage is defined between each pair of adjacent first spaced-apart barriers. The other jig member defines second receiving passages for receiving the first spaced-apart barriers respectively. A second spaced-apart barrier is defined between every two adjacent second receiving passages to space the two adjacent second receiving passages apart. The second spaced-apart barriers are inserted in the first receiving passages respectively.Type: ApplicationFiled: November 6, 2007Publication date: May 7, 2009Applicant: Cheng Uei Precision Industry Co., Ltd.Inventors: Ming-Chia Chi, Chih-Cheng Wu, Yu-Tso Liu, Chin-Chiang Li, Yu-Hua Hsieh
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Publication number: 20080303533Abstract: A cable testing device of the present invention can test sheltering performance of a cable which has a central wire, a shelter wrapped around the central wire and an exterior cover wrapped around the shelter. One end of the central wire and two ends of the shelter are earthed. The cable testing device includes a network testing device and a metal tube. The network testing device has an input which is connected to the other end of the cable and an output. The metal tube incloses the cable to be tested, one end of the metal tube is connected to the output of the network testing device, the other end is earthed. As a result, an electromagnetic field is formed in the interior of metal tube, thereby, the sheltering performance of the shelter of the cable can be tested directly before the whole cable product being assembled.Type: ApplicationFiled: June 7, 2007Publication date: December 11, 2008Inventors: Chih-Cheng Wu, Chin-Chiang Li, Yu-Hua Hsieh, Hsing-Hua Hsieh
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Publication number: 20080054447Abstract: A digital camera module (200) includes a chip package (20) and a lens module (50) mounted to the chip package. The package includes a carrier (21), a chip (23), a plurality of wires (24), a supporting member (25), an adhesive (26), and a cover (28). The carrier has a top surface (211), and a plurality of top contacts (215) arranged on the top surface. The chip is mounted to the top surface of the carrier, and includes an active area (231) and a plurality of pads (233). The wires electrically respectively connect one of the pads to a corresponding top contact. The adhesive is applied to a peripheral circumference of the top surface of the chip. The cover is adhered to the adhesive, and closes the active area of the chip. The supporting member is disposed between the carrier and the cover to support the cover.Type: ApplicationFiled: December 27, 2006Publication date: March 6, 2008Applicant: ALTUS TECHNOLOGY INC.Inventors: CHIH-CHENG WU, CHANG-KUO YANG, MING LEE
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Publication number: 20080023808Abstract: A digital camera module (10) includes a chip package (20) and a lens module (50) mounted to the chip package. The package includes a carrier (21), a chip (23), a plurality of wires (24), an adhesive (26) and a cover (28). The carrier has a cavity (213) defined therein, an opening defined in a top surface, and a plurality of top contacts (215) arranged on the top surface around the opening. The chip is received in the cavity, and includes an active area (231) and a plurality of pads (233) disposed on a top surface thereof. The wires electrically connect each of the pads to a corresponding top contact of the carrier. The adhesive is applied to a peripheral circumference of the top surface of the chip around the active area. The cover is adhered to the adhesive, and encloses the active area of the chip cooperatively with the adhesive.Type: ApplicationFiled: December 27, 2006Publication date: January 31, 2008Applicant: ALTUS TECHNOLOGY INC.Inventors: CHIH-CHENG WU, CHANG-KUO YANG