Patents by Inventor Chih-Cheng Yeh

Chih-Cheng Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154447
    Abstract: A power system including a first battery pack, a second battery pack, and a power management circuit is disclosed. The first battery pack has a first end and a second end, and has a first battery capacity. The second battery pack has a third end and a fourth end. The third end is coupled to the second end of the first battery pack and provides a low battery voltage. The fourth end is grounded, the second battery pack has a second battery capacity, and the second battery capacity is greater than the first battery capacity. The power management circuit is coupled to the second battery pack to receive the low battery voltage, and provides a component operating voltage to an electronic components based on the low battery voltage.
    Type: Application
    Filed: August 29, 2023
    Publication date: May 9, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Yi-Hsuan Lee, Liang-Cheng Kuo, Chun-Wei Ko, Ya Ju Cheng, Chih Wei Huang, Ywh Woei Yeh, Yu Cheng Lin, Yen Ting Wang
  • Publication number: 20240128211
    Abstract: Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.
    Type: Application
    Filed: April 27, 2023
    Publication date: April 18, 2024
    Inventors: Chih-Wei WU, An-Jhih SU, Hua-Wei TSENG, Ying-Ching SHIH, Wen-Chih CHIOU, Chun-Wei CHEN, Ming Shih YEH, Wei-Cheng WU, Der-Chyang YEH
  • Patent number: 6848758
    Abstract: A DIY cabinet has a foldable frame, a top panel, a bottom panel, a rear panel and multiple pop-it fasteners. The panels are attached to the foldable frame with the pop-it fasteners. Each pop-it fastener is composed of a countersunk tube and a stud. The countersunk tubes are pressed into head holes in panels, and the studs are screwed into and extend from base holes in the foldable frame and align with corresponding head holes in the panels. The studs extending from the base holes are pressed respectively into the countersunk tube in the head holes. Thereby, the panels are conveniently mounted on the foldable frame without using any tools. Moreover, the foldable frame can be folded to reduce the size of the disassembled DIY cabinet.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: February 1, 2005
    Inventors: Chih-Cheng Yeh, Nan-Chang Liang