Patents by Inventor Chih-Cherng Jeng
Chih-Cherng Jeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8951826Abstract: A backside illuminated CMOS image sensor comprises an extended photo active region formed over a substrate using a first high energy ion implantation process and an isolation region formed over the substrate using a second high energy ion implantation process. The extended photo active region is enclosed by the isolation region, which has a same depth as the extended photo active region. The extended photo active region helps to increase the number of photons converted into electrons so as to improve quantum efficiency.Type: GrantFiled: March 23, 2012Date of Patent: February 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Chi Jeng, Chih-Cherng Jeng, Chih-Kang Chao, Ching-Hwanq Su, Yan-Hua Lin, Yu-Shen Shih
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Patent number: 8889461Abstract: A method includes performing a first epitaxy to grow a first epitaxy layer of a first conductivity type, and performing a second epitaxy to grow a second epitaxy layer of a second conductivity type opposite the first conductivity type over the first epitaxy layer. The first and the second epitaxy layers form a diode. The method further includes forming a gate dielectric over the first epitaxy layer, forming a gate electrode over the gate dielectric, and implanting a top portion of the first epitaxy layer and the second epitaxy layer to form a source/drain region adjacent to the gate dielectric.Type: GrantFiled: September 14, 2012Date of Patent: November 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shiu-Ko JangJian, Min Hao Hong, Kei-Wei Chen, Chih-Cherng Jeng
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Patent number: 8872301Abstract: The presented principles describe an apparatus and method of making the same, the apparatus being a semiconductor circuit device, having shallow trench isolation features bounding an active area and a periphery area on a semiconductor substrate to electrically isolate structures in the active area from structures in the periphery area. The shallow trench isolation feature bounding the active area is shallower than the shallow trench isolation feature bounding the periphery area, with the periphery area shallow trench isolation structure being formed through two or more etching steps.Type: GrantFiled: April 24, 2012Date of Patent: October 28, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Yang Hung, Po-Zen Chen, Szu-Hung Yang, Chih-Cherng Jeng, Chih-Kang Chao, I-I Cheng
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Patent number: 8860101Abstract: A system and method for reducing cross-talk between photosensitive diodes is provided. In an embodiment an isolation region comprising a first concentration of dopants is located between the photosensitive diodes. The photosensitive diodes have a second concentration of dopants that is less than the first concentration of dopants, which helps to prevent diffusion from the photosensitive diodes to form a potential path for undesired cross-talk between the photosensitive diodes.Type: GrantFiled: February 27, 2012Date of Patent: October 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lan Fang Chang, Ching-Hwanq Su, Wei-Ming You, Chih-Cherng Jeng, Chih-Kang Chao, Fu-Sheng Guo
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Patent number: 8803271Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed on the front side of the semiconductor substrate. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the dielectric layer is over a back surface of the semiconductor substrate. A metal shield is over the dielectric layer and overlapping the photo-sensitive device. A metal plug penetrates through the dielectric layer, wherein the metal plug electrically couples the metal shield to the semiconductor substrate.Type: GrantFiled: March 23, 2012Date of Patent: August 12, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhe-Ju Liu, Chih-Cherng Jeng, Kuo-Cheng Lee, Szu-Hung Yang, Po-Zen Chen, Chi-Chin Hsu
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Patent number: 8652868Abstract: An implanting method for forming a photodiode comprises providing a substrate with a first conductivity, growing an epitaxial layer on the substrate, implanting ions with a second conductivity in the epitaxial layer from a front side of the substrate and implanting ions with the first conductivity in the epitaxial layer from the front side of the substrate to form a photo active region adjacent to the front side and a photo inactive region underneath the photo active region. By employing the implanting method, an average doping density of the photo active region is approximately ten times more than an average doping density of the photo inactive region.Type: GrantFiled: March 1, 2012Date of Patent: February 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Shen Shih, Ching-Hwanq Su, Wei-Ming You, Chih-Cherng Jeng, Kuo-Cheng Lee, Yen-Hsung Ho
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Patent number: 8628998Abstract: A method includes performing a grinding on a backside of a semiconductor substrate. An image sensor is disposed on a front side of the semiconductor substrate. An impurity is doped into a surface layer of the backside of the semiconductor substrate to form a doped layer. A multi-cycle laser anneal is performed on the doped layer.Type: GrantFiled: May 22, 2012Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ting Lin, Cheng-Jung Sung, Yu-Sheng Wang, Shiu-Ko JangJian, Wei-Ming You, Chih-Cherng Jeng, Ching-Hwanq Su
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Publication number: 20130320419Abstract: A method includes performing a first epitaxy to grow a first epitaxy layer of a first conductivity type, and performing a second epitaxy to grow a second epitaxy layer of a second conductivity type opposite the first conductivity type over the first epitaxy layer. The first and the second epitaxy layers form a diode. The method further includes forming a gate dielectric over the first epitaxy layer, forming a gate electrode over the gate dielectric, and implanting a top portion of the first epitaxy layer and the second epitaxy layer to form a source/drain region adjacent to the gate dielectric.Type: ApplicationFiled: September 14, 2012Publication date: December 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shiu-Ko JangJian, Min Hao Hong, Kei-Wei Chen, Chih-Cherng Jeng
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Publication number: 20130277790Abstract: The presented principles describe an apparatus and method of making the same, the apparatus being a semiconductor circuit device, having shallow trench isolation features bounding an active area and a periphery area on a semiconductor substrate to electrically isolate structures in the active area from structures in the periphery area. The shallow trench isolation feature bounding the active area is shallower than the shallow trench isolation feature bounding the periphery area, with the periphery area shallow trench isolation structure being formed through two or more etching steps.Type: ApplicationFiled: April 24, 2012Publication date: October 24, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Yang Hung, Po-Zen Chen, Szu-Hung Yang, Chih-Cherng Jeng, Chih-Kang Chao, I-I Cheng
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Publication number: 20130230941Abstract: An implanting method for forming a photodiode comprises providing a substrate with a first conductivity, growing an epitaxial layer on the substrate, implanting ions with a second conductivity in the epitaxial layer from a front side of the substrate and implanting ions with the first conductivity in the epitaxial layer from the front side of the substrate to form a photo active region adjacent to the front side and a photo inactive region underneath the photo active region. By employing the implanting method, an average doping density of the photo active region is approximately ten times more than an average doping density of the photo inactive region.Type: ApplicationFiled: March 1, 2012Publication date: September 5, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Shen Shih, Ching-Hwanq Su, Wei-Ming You, Chih-Cherng Jeng, Kuo-Cheng Lee, Yen-Hsung Ho
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Publication number: 20130207220Abstract: A system and method for reducing cross-talk between photosensitive diodes is provided. In an embodiment an isolation region comprising a first concentration of dopants is located between the photosensitive diodes. The photosensitive diodes have a second concentration of dopants that is less than the first concentration of dopants, which helps to prevent diffusion from the photosensitive diodes to form a potential path for undesired cross-talk between the photosensitive diodes.Type: ApplicationFiled: February 27, 2012Publication date: August 15, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lan Fang Chang, Ching-Hwanq Su, Wei-Ming You, Chih-Cherng Jeng, Chih-Kang Chao, Fu-Sheng Guo
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Publication number: 20130193539Abstract: A backside illuminated CMOS image sensor comprises an extended photo active region formed over a substrate using a first high energy ion implantation process and an isolation region formed over the substrate using a second high energy ion implantation process. The extended photo active region is enclosed by the isolation region, which has a same depth as the extended photo active region. The extended photo active region helps to increase the number of photons converted into electrons so as to improve quantum efficiency.Type: ApplicationFiled: March 23, 2012Publication date: August 1, 2013Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Jung-Chi Jeng, Chih-Cherng Jeng, Chih-Kang Chao, Ching-Hwanq Su, Yan-Hua Lin, Yu-Shen Shih
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Publication number: 20130171766Abstract: A method includes performing a grinding on a backside of a semiconductor substrate. An image sensor is disposed on a front side of the semiconductor substrate. An impurity is doped into a surface layer of the backside of the semiconductor substrate to form a doped layer. A multi-cycle laser anneal is performed on the doped layer.Type: ApplicationFiled: May 22, 2012Publication date: July 4, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Ting Lin, Cheng-Jung Sung, Yu-Sheng Wang, Shiu-Ko JangJian, Wei-Ming You, Chih-Cherng Jeng, Ching-Hwanq Su
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Patent number: 8049213Abstract: A method of measuring dimensional characteristics includes providing a substrate and forming a reflective layer over the substrate. A dielectric layer is then formed over the reflective layer. The dielectric layer includes a grating pattern and a resistivity test line inset in a transparent region. Radiation is then directed onto the dielectric layer so that some of the radiation is transmitted through the transparent region to the reflective layer. A radiation pattern is then detected from the radiation reflected and scattered by the metal grating pattern. The radiation pattern is analyzed to determine a first dimensional information. Then the resistance of the resistivity test line is measured, and that resistance is analyzed to determine a second dimensional information. The first and second dimensional informations are then compared.Type: GrantFiled: December 18, 2007Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Chung Su, Yi-Wei Chiu, Tzu Chan Weng, Yih Song Chiu, Pin Chia Su, Chih-Cherng Jeng, Kuo-Hsiu Wei
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Patent number: 7777338Abstract: A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.Type: GrantFiled: September 13, 2004Date of Patent: August 17, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Hsiang Yao, Tai-Chun Huang, Kuan-Shou Chi, Chih-Cherng Jeng, Ming-Shuoh Liang, Wen-Kai Wan, Chin-Chiu Hsia
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Publication number: 20090152545Abstract: A method of measuring dimensional characteristics includes providing a substrate and forming a reflective layer over the substrate. A dielectric layer is then formed over the reflective layer. The dielectric layer includes a grating pattern and a resistivity test line inset in a transparent region. Radiation is then directed onto the dielectric layer so that some of the radiation is transmitted through the transparent region to the reflective layer. A radiation pattern is then detected from the radiation reflected and scattered by the metal grating pattern. The radiation pattern is analyzed to determine a first dimensional information. Then the resistance of the resistivity test line is measured, and that resistance is analyzed to determine a second dimensional information. The first and second dimensional informations are then compared.Type: ApplicationFiled: December 18, 2007Publication date: June 18, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Chung Su, Yi-Wei Chiu, Tzu-Chan Weng, Yih Song Chiu, Pin Chia Su, Chih-Cherng Jeng, Kuo-Hsiu Wei
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Publication number: 20060055002Abstract: A wafer device is disclosed for improving reliability of circuits fabricated in an active area on a silicon substrate. A seal ring is fabricated around the active area, and a shallow trench isolation is also formed between the seal ring and a scribe line by etching into a portion of the silicon substrate, wherein the seal ring and the shallow trench isolation prevent die saw induced crack from propagating to the active area when the active area is cut along the scribe line.Type: ApplicationFiled: August 3, 2005Publication date: March 16, 2006Inventors: Chih-Hsiang Yao, Wen-Kai Wan, Kuan-Shou Chi, Chih-Cherng Jeng, Ming-Shuo Liang, Tai-Chun Huang, Chin-Chiu Hsia, Mong-Song Liang
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Publication number: 20060055007Abstract: A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.Type: ApplicationFiled: September 13, 2004Publication date: March 16, 2006Inventors: Chih-Hsiang Yao, Tai-Chun Huang, Kuan-Shou Chi, Chih-Cherng Jeng, Ming-Shuoh Liang, Wen-Kai Wan, Chin-Chiu Hsia
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Publication number: 20040004235Abstract: A vertical nanotube transistor and a process for fabricating the same. First, a source layer and a catalyst layer are successively formed on a substrate. A dielectric layer is formed on the catalyst layer and the substrate. Next, the dielectric layer is selectively removed to form a first dielectric mesa, a gate dielectric layer spaced apart from the first dielectric mesa by a first opening, and a second dielectric mesa spaced apart from the gate dielectric layer by a second opening. Next, a nanotube layer is formed in the first opening. Finally, a drain layer is formed on the nanotube layer and the first dielectric mesa, and a gate layer is formed in the second opening. The formation position of the nanotubes can be precisely controlled.Type: ApplicationFiled: November 22, 2002Publication date: January 8, 2004Inventors: Chun-Tao Lee, Lin-Hung Shiu, Chih-Cherng Jeng, Wen-Ti Lin, Wei-Su Chen