Patents by Inventor Chih-Chi Chang

Chih-Chi Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200215643
    Abstract: Aspects relate to systems, methods, and apparatus for a manufacturing tool. The manufacturing tool is comprised of a vacuum tool and an ultrasonic welder as a unified manufacturing tool. The manufacturing tool may be used to pick and position a manufacturing part that is then welded with the associated ultrasonic welder.
    Type: Application
    Filed: March 18, 2020
    Publication date: July 9, 2020
    Inventors: Patrick Conall Regan, Chih-Chi Chang, Kuo-Hung Lee, Ming-Feng Jean
  • Patent number: 10700275
    Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode via and a bottom electrode over a top of the bottom electrode via. A data storage layer is over the bottom electrode and a top electrode is over the data storage layer. A top electrode via is on an upper surface of the top electrode and is centered along a first line that is laterally offset from a second line centered upon a bottommost surface of the bottom electrode via. The first line is perpendicular to the upper surface of the top electrode and parallel to the second line.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yang Chang, Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You
  • Patent number: 10700176
    Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
  • Patent number: 10667581
    Abstract: Manufacturing and assembly of a shoe or a portion of a shoe is enhanced by automated placement and assembly of shoe parts. For example, a part-recognition system analyzes an image of a shoe part to identify the part and determine a location of the part. Once the part is identified and located, the part can be manipulated by an automated manufacturing tool.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: June 2, 2020
    Assignee: NIKE, Inc.
    Inventors: Patrick Conall Regan, Kuo-Hung Lee, Chih-Chi Chang, Ming-Feng Jean, Chang-Chu Liao
  • Publication number: 20200168574
    Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.
    Type: Application
    Filed: April 23, 2019
    Publication date: May 28, 2020
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 10666153
    Abstract: A control method for a power convert is disclosed. The power convert uses an active-clamp flyback topology and has low-side and high-side switches. The low-side switch is switched to generate consecutive switching cycles including a modified flyback cycle and a normal flyback cycle. Each of the consecutive switching cycles is not less than a blanking time generated in response to a load of the power converter. The high-side switch is constantly turned OFF during the normal flyback cycle. The high-side switch is turned ON after the blanking time during the modified flyback cycle to perform zero-voltage switching for the low-side switch.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: May 26, 2020
    Assignee: LEADTREND TECHNOLOGY CORPORATION
    Inventors: Yao Tsung Chen, Chih Chi Chang, Meng Jen Tsai
  • Patent number: 10651183
    Abstract: A manufacturing method of a semiconductor device includes: providing a substrate having memory and high voltage regions; sequentially forming a floating gate layer and a hard mask layer on the substrate; patterning the hard mask layer to form a first opening exposing a portion of the floating gate layer in the range of the memory region; patterning the hard mask layer and the floating gate layer to form a second opening overlapped with the high voltage region; performing a first thermal growth process to simultaneously form a first oxide structure on the portion of the floating gate layer exposed by the first opening, and to form a second oxide structure on a portion of the substrate overlapped with the second opening; removing the hard mask layer; and patterning the floating gate layer by using the first oxide structure as a mask.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 12, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Jianjun Yang, Cheng-Hua Yang, Fan-Chi Meng, Chih-Chien Chang, Shen-De Wang
  • Publication number: 20200143091
    Abstract: A tool path for treating a shoe upper may be generated to treat substantially only the surface of the shoe bounded by a bite line. The bite line may be defined to correspond to the junction of the shoe upper and a shoe bottom unit. Bite line data and three-dimensional profile data representing at least a portion of a surface of a shoe upper bounded by a bite line may be utilized in combination to generate a tool path for processing the surface of the upper, such as automated application of adhesive to the surface of a lasted upper bounded by a bite line.
    Type: Application
    Filed: January 2, 2020
    Publication date: May 7, 2020
    Inventors: Patrick Conall Regan, Dragan Jurkovic, Chih-Chi Chang, Ming-Feng Jean
  • Publication number: 20200143868
    Abstract: The present disclosure provides a memory control circuit configured to precede a data-reading process with a memory. For the data-reading process, the memory transmits a DQ and a DQS indicating a time to read the DQ. The DQS includes a preamble. The memory control circuit includes a control circuit and a sampling circuit. The control circuit is configured to generate an enabling signal. The sampling circuit coupled to the control circuit is configured to sample the DQS based on the enabling signal in order to determine a sampling level. The control circuit determines whether the sampling level matches a signal level of the preamble or not.
    Type: Application
    Filed: November 1, 2018
    Publication date: May 7, 2020
    Inventors: Chun-Chi YU, Gerchih Chou, Chih-Wei Chang, Shen-Kuo Huang
  • Patent number: 10643685
    Abstract: The present disclosure provides a memory control circuit configured to precede a data-reading process with a memory. For the data-reading process, the memory transmits a DQ and a DQS indicating a time to read the DQ. The DQS includes a preamble. The memory control circuit includes a control circuit and a sampling circuit. The control circuit is configured to generate an enabling signal. The sampling circuit coupled to the control circuit is configured to sample the DQS based on the enabling signal in order to determine a sampling level. The control circuit determines whether the sampling level matches a signal level of the preamble or not.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 5, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-Chi Yu, Gerchih Chou, Chih-Wei Chang, Shen-Kuo Huang
  • Publication number: 20200129753
    Abstract: A wireless physical stimulation system includes at least one sensor, at least one physical stimulation device and an electronic device. The electronic device wirelessly connects to the at least one sensor disposed on a human body and the at least one physical stimulation device disposed on the human body. The at least one sensor is configured to sense at least one first sensing signal. The electronic device is configured to receive the least one sensing signal from the least one sensor; generate first body condition information on the basis of a body condition identifying model and according to the least one sensing signal; generate first feedback plan information on the basis of a first feedback model and according to the first body information; and control the at least one physical stimulation device according to the first feedback plan information.
    Type: Application
    Filed: November 28, 2018
    Publication date: April 30, 2020
    Inventors: Chih-Yun LIU, An-Chun CHEN, Ya-Chi CHANG, Shih-Yao WEI, Tse-Yu LIN
  • Publication number: 20200130138
    Abstract: Provided herein are chemical-mechanical planarization (CMP) systems and methods to reduce metal particle pollution on dressing disks and polishing pads. Such methods may include contacting a dressing disk and at least one conductive element with an electrolyte solution and applying direct current (DC) power to the dressing disk and the at least one conductive element.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 30, 2020
    Inventors: Chih-Chieh CHANG, Yen-Ting CHEN, Hui-Chi HUANG, Kei-Wei CHEN
  • Publication number: 20200133061
    Abstract: A polarizer substrate includes a substrate, an organic planarization layer, an inorganic buffer layer, and a plurality of strip-shaped polarizer structures. The organic planarization layer is located on the substrate. The inorganic buffer layer is located on the organic planarization layer. The inorganic buffer layer has a plurality of trenches located on a first surface. The trenches do not penetrate through the inorganic buffer layer. The strip-shaped polarizer structures are located on the first surface of the inorganic buffer layer. Each of the trenches is located between two adjacent polarizer structures. A display panel is also provided.
    Type: Application
    Filed: May 9, 2019
    Publication date: April 30, 2020
    Applicant: Au Optronics Corporation
    Inventors: Tsai-Sheng Lo, Chih-Chiang Chen, Ming-Jui Wang, Sheng-Kai Lin, Sheng-Ming Huang, Chia-Hsin Chung, Hui-Ku Chang, Wei-Chi Wang, Jen-Kuei Lu
  • Patent number: 10636787
    Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy semiconductor fins on a substrate. The dummy semiconductor fins are adjacent to each other and are grouped into a plurality of fin groups. The dummy semiconductor fins of the fin groups are recessed one group at a time.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Po-Chi Wu, Chih-Han Lin, Horng-Huei Tseng
  • Publication number: 20200126976
    Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Yu CHEN, Chih-Ping CHAO, Chun-Hung CHEN, Chung-Long CHANG, Kuan-Chi TSAI, Wei-Kung TSAI, Hsiang-Chi CHEN, Ching-Chung HSU, Cheng-Chang HSU, Yi-Sin WANG
  • Patent number: 10630289
    Abstract: An ODT circuit is connected to a memory module and includes a first transmission line, a first ODT, a second ODT, a first switch circuit, a third ODT, a fourth ODT, a second switch circuit, and an ODT control logic. The first and second ODTs are coupled to a first node on the first transmission line. The first switch circuit includes a first switch and a second switch, and is driven according to the first control signal. The third and the fourth ODTs are coupled to a second node on the first transmission line. The second switch circuit includes a third switch and a fourth switch, and is driven according to the second control signal. The ODT control logic outputs the first control signal and the second control signal to control the first switch circuit and the second switch circuit to be turned on at different timings.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: April 21, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Shen-Kuo Huang, Chun-Chi Yu, Chih-Wei Chang, Gerchih Chou
  • Patent number: 10610958
    Abstract: Aspects relate to systems, methods, and apparatus for a manufacturing tool. The manufacturing tool is comprised of a vacuum tool and an ultrasonic welder as a unified manufacturing tool. The manufacturing tool may be used to pick and position a manufacturing part that is then welded with the associated ultrasonic welder.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: April 7, 2020
    Assignee: NIKE, INC.
    Inventors: Patrick Conall Regan, Chih-Chi Chang, Kuo-Hung Lee, Ming-Feng Jean
  • Publication number: 20200106368
    Abstract: A control method for a power convert is disclosed. The power convert uses an active-clamp flyback topology and has low-side and high-side switches. The low-side switch is switched to generate consecutive switching cycles including a modified flyback cycle and a normal flyback cycle. Each of the consecutive switching cycles is not less than a blanking time generated in response to a load of the power converter. The high-side switch is constantly turned OFF during the normal flyback cycle. The high-side switch is turned ON after the blanking time during the modified flyback cycle to perform zero-voltage switching for the low-side switch.
    Type: Application
    Filed: August 23, 2019
    Publication date: April 2, 2020
    Inventors: Yao Tsung CHEN, Chih Chi CHANG, Meng Jen TSAI
  • Publication number: 20200103572
    Abstract: A polarizer substrate and manufacturing method thereof are provided. The polarizer substrate includes a substrate, a plurality of polarizer structures, a plurality of barrier structures, and a passivation layer. The polarizer structures are disposed on the substrate. Each of the polarizer structures includes a wire-grid and a capping structure disposed on the wire-grid. The barrier structures are disposed on the capping structures and not contacting with the side walls of the wire-grids. A gap between two adjacent barrier structures is smaller than a gap between two adjacent wire-grids. The passivation layer is disposed on the barrier structures.
    Type: Application
    Filed: May 14, 2019
    Publication date: April 2, 2020
    Applicant: Au Optronics Corporation
    Inventors: Wei-Chi Wang, Chih-Chiang Chen, Tsai-Sheng Lo, Sheng-Kai Lin, Chia-Hsin Chung, Hui-Ku Chang, Ming-Jui Wang, Sheng-Ming Huang, Jen-Kuei Lu
  • Publication number: 20200105533
    Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 2, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu CHEN, Yu-Chi LU, Chih-Pin TSAO, Shih-Hsun CHANG