Patents by Inventor Chih-Chi Cheng

Chih-Chi Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948975
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.
    Type: Grant
    Filed: October 24, 2021
    Date of Patent: April 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
  • Patent number: 11941298
    Abstract: A host system initiates an abort of a command that has been placed into a submission queue (SQ) of the host system. The host system identifies at least one of a first outcome and a second outcome. When the first outcome indicates that the command is not completed and the second outcome indicates that the SQ entry has been fetched from the SQ, the host system sends an abort request to a storage device, and issues a cleanup request to direct the host controller to reclaim host hardware resources allocated to the command. The host system adds a completion queue (CQ) entry to a CQ and sets an overall command status (OCS) value of the CQ entry based on at least one of the first outcome and the second outcome.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: March 26, 2024
    Assignee: MediaTek Inc.
    Inventors: Chih-Chieh Chou, Chia-Chun Wang, Liang-Yen Wang, Chin Chin Cheng, Szu-Chi Liu
  • Patent number: 11256894
    Abstract: In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: February 22, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Wesley James Holland, Rashmi Kulkarni, Ling Feng Huang, Huang Huang, Jeffrey Shabel, Chih-Chi Cheng, Satish Anand, Songhe Cai, Simon Peter William Booth, Bohuslav Rychlik
  • Patent number: 11140375
    Abstract: In some aspects, the present disclosure provides a method for sharing a single optical sensor between multiple image processors. In some embodiments, the method includes receiving, at a control arbiter, a first desired configuration of a first one or more desired configurations for capturing an image frame by the optical sensor, the first one or more desired configurations communicated from a primary image processor. The method may also include receiving, at the control arbiter, a second desired configuration of a second one or more desired configurations for capturing the image frame by the optical sensor, the second one or more desired configurations communicated from a secondary image processor. The method may also include determining, by the control arbiter, an actual configuration for capturing the image frame by the optical sensor, the actual configuration based on the first desired configuration and the second desired configuration.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 5, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Wesley James Holland, Satish Goverdhan, Venkata Rajesh Kumar Sastrula, Ramesh Ramaswamy, Songhe Cai, Ling Feng Huang, Chih-Chi Cheng, Huang Huang, Rajakumar Govindaram
  • Publication number: 20210195159
    Abstract: In some aspects, the present disclosure provides a method for sharing a single optical sensor between multiple image processors. In some embodiments, the method includes receiving, at a control arbiter, a first desired configuration of a first one or more desired configurations for capturing an image frame by the optical sensor, the first one or more desired configurations communicated from a primary image processor. The method may also include receiving, at the control arbiter, a second desired configuration of a second one or more desired configurations for capturing the image frame by the optical sensor, the second one or more desired configurations communicated from a secondary image processor. The method may also include determining, by the control arbiter, an actual configuration for capturing the image frame by the optical sensor, the actual configuration based on the first desired configuration and the second desired configuration.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Inventors: Wesley James HOLLAND, Satish GOVERDHAN, Venkata Rajesh Kumar SASTRULA, Ramesh RAMASWAMY, Songhe CAI, Ling Feng HUANG, Chih-Chi CHENG, Huang HUANG, Rajakumar GOVINDARAM
  • Publication number: 20210174047
    Abstract: In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.
    Type: Application
    Filed: December 4, 2019
    Publication date: June 10, 2021
    Inventors: Wesley James HOLLAND, Rashmi KULKARNI, Ling Feng HUANG, Huang HUANG, Jeffrey SHABEL, Chih-Chi CHENG, Satish ANAND, Songhe CAI, Simon Peter William BOOTH, Bohuslav RYCHLIK
  • Patent number: 10861855
    Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: December 8, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Cheng Tsai, Chih-Chi Cheng, Chia-Wei Wu, Ger-Pin Lin
  • Publication number: 20200235101
    Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.
    Type: Application
    Filed: April 7, 2020
    Publication date: July 23, 2020
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Cheng Tsai, Chih-Chi Cheng, Chia-Wei Wu, Ger-Pin Lin
  • Patent number: 10658365
    Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: May 19, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Cheng Tsai, Chih-Chi Cheng, Chia-Wei Wu, Ger-Pin Lin
  • Publication number: 20190313026
    Abstract: Methods, systems, and devices for image processing are described. A device may include a plurality of buffer components, each of which may receive a pixel lines that may each be associated with a respective raw image. An arbitration component of the device may combine at least some of the pixel lines into one or more data packets. The arbitration component may pass, using an arbitration scheme such as a time division multiplexing scheme, the one or more data packets from the arbitration component to a shared image signal processor (ISP) of the device. The shared ISP may generate a respective processed image based at least in part on the one or more data packets. In some examples, the device may maintain a respective set of image statistics, registers, and the like for at least some of the raw images.
    Type: Application
    Filed: April 9, 2018
    Publication date: October 10, 2019
    Inventors: Scott Cheng, Chih-Chi Cheng, Pawan Kumar Baheti, Michael Lee Coulter, Maulesh Patel, John Welch, Krishnam Indukuri
  • Publication number: 20190081047
    Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.
    Type: Application
    Filed: August 2, 2018
    Publication date: March 14, 2019
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Cheng Tsai, Chih-Chi Cheng, Chia-Wei Wu, Ger-Pin Lin
  • Patent number: 10151048
    Abstract: A manufacturing method of an epitaxial contact structure in a semiconductor memory device includes the following steps. A recess is formed in a semiconductor substrate by an etching process. An etching defect is formed in the recess by the etching process. An oxidation process is performed after the etching process. An oxide layer is formed in the recess by the oxidation process, and the etching defect is encompassed by the oxide layer. A cleaning process is performed after the oxidation process. The oxide layer and the etching defect encompassed by the oxide layer are removed by the cleaning process. An epitaxial growth process is performed to form an epitaxial contact structure in the recess after the cleaning process.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: December 11, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Wan-Chi Wu, Hui-Ling Chuang, Chih-Chi Cheng, Chiu-Hsien Yeh, Chien-Cheng Tsai, Hung-Jung Yan
  • Publication number: 20180114296
    Abstract: A method performed by an electronic device is described. The method includes obtaining an input image. The input image includes image noise. The method also includes removing the image noise from the input image to produce a noise-removed image. The method further includes avoiding enhancing the image noise by performing edge detection on the noise-removed image to produce edge information. The method additionally includes producing a processed image based on the input image and the edge information.
    Type: Application
    Filed: October 21, 2016
    Publication date: April 26, 2018
    Inventors: Shang-Chih Chuang, Xianbiao Shu, Xiaoyun Jiang, Tao Ma, Chih-Chi Cheng
  • Patent number: 9934153
    Abstract: A patch memory system for accessing patches from a memory is disclosed. A patch is an abstraction that refers to a contiguous, array of data that is a subset of an N-dimensional array of data. The patch memory system includes a tile cache, and is configured to fetch data associated with a patch by determining one or more tiles associated with an N-dimensional array of data corresponding to the patch, and loading data for the one or more tiles from the memory into the tile cache. The N-dimensional array of data may be a two-dimensional (2D) digital image comprising a plurality of pixels. A patch of the 2D digital image may refer to a 2D subset of the image.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 3, 2018
    Assignee: NVIDIA Corporation
    Inventors: Jason Lavar Clemons, Chih-Chi Cheng, Daniel Robert Johnson, Stephen William Keckler, Iuri Frosio, Yun-Ta Tsai
  • Publication number: 20170004089
    Abstract: A patch memory system for accessing patches from a memory is disclosed. A patch is an abstraction that refers to a contiguous, array of data that is a subset of an N-dimensional array of data. The patch memory system includes a tile cache, and is configured to fetch data associated with a patch by determining one or more tiles associated with an N-dimensional array of data corresponding to the patch, and loading data for the one or more tiles from the memory into the tile cache. The N-dimensional array of data may be a two-dimensional (2D) digital image comprising a plurality of pixels. A patch of the 2D digital image may refer to a 2D subset of the image.
    Type: Application
    Filed: June 30, 2015
    Publication date: January 5, 2017
    Inventors: Jason Lavar Clemons, Chih-Chi Cheng, Daniel Robert Johnson, Stephen William Keckler, Iuri Frosio, Yun-Ta Tsai
  • Patent number: 9183430
    Abstract: A portable electronic apparatus and an interactive human face login method are disclosed. The portable electronic apparatus comprises a face database, a user interface, an image capturing device, and a recognition circuit. The face database stores a plurality of facial expression feature information. The user interface randomly generates a plurality of facial expression indications used for guiding a user to sequentially show a plurality of facial expressions. The image capturing device captures the facial expressions to output a plurality of facial expression images. The recognition circuit receives a login request and determines whether the facial expressions are consistent with the facial expression indications according to the facial expression feature information and the facial expression images. The login request is allowed if the facial expressions are consistent with the facial expression indications.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: November 10, 2015
    Assignee: QUANTA COMPUTER INC.
    Inventors: Po-Chi Huang, Chih-Chi Cheng
  • Patent number: 9131160
    Abstract: A method for controlling an exposure duration of a high dynamic range image, including: consecutively generating a first high dynamic range image having a first exposure duration ratio and a second high dynamic range image having a second exposure duration ratio greater than the first exposure duration ratio; performing image quality evaluations on both the first high dynamic range image and the second high dynamic range image to obtain a first image quality and a second image quality, respectively; and determining whether the second image quality is better than the first image quality; if yes, generating a third high dynamic range image having a third exposure duration ratio greater than the second exposure duration ratio; if not, generating the third high dynamic range image having the first exposure duration ratio and setting the first exposure duration ration as the optimal exposure duration ratio.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: September 8, 2015
    Assignee: QUANTA COMPUTER INC.
    Inventors: Keng-Sheng Lin, Chih-Chi Cheng, Chung-Te Li, Hsin-Yu Chen, Wen-Chu Yang
  • Patent number: 9116573
    Abstract: A virtual control device is provided for an electronic device. The virtual control device includes a first lens, a second lens, a first photosensitive unit, a second photosensitive unit and a processor unit. The first photosensitive unit is arranged behind the first lens by a focal length, and obtains a first image via the first lens. The second photosensitive unit is arranged behind the second lens by the focal length, and obtains a second image via the second lens. The processor unit determines the object-position coordinates of a virtual control plane according to a first position of the projection of the object on the first photosensitive unit and a second position of the projection of the object on the second photosensitive unit, and the processor unit provides the object-position coordinates to the electronic device.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: August 25, 2015
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chih-Chi Cheng, Chee-Chun Leung, Wei-Min Chao
  • Publication number: 20150042836
    Abstract: A method for controlling an exposure duration of a high dynamic range image, including: consecutively generating a first high dynamic range image having a first exposure duration ratio and a second high dynamic range image having a second exposure duration ratio greater than the first exposure duration ratio; performing image quality evaluations on both the first high dynamic range image and the second high dynamic range image to obtain a first image quality and a second image quality, respectively; and determining whether the second image quality is better than the first image quality; if yes, generating a third high dynamic range image having a third exposure duration ratio greater than the second exposure duration ratio; if not, generating the third high dynamic range image having the first exposure duration ratio and setting the first exposure duration ration as the optimal exposure duration ratio.
    Type: Application
    Filed: November 6, 2013
    Publication date: February 12, 2015
    Applicant: Quanta Computer Inc.
    Inventors: Keng-Sheng Lin, Chih-Chi Cheng, Chung-Te Li, Hsin-Yu Chen, Wen-Chu Yang
  • Publication number: 20150035726
    Abstract: An eye-accommodation-aware head mounted visual assistant system and an imaging method thereof are disclosed. The eye-accommodation-aware head mounted visual assistant system comprises a beam splitter, a projecting light source, an image sensor, a calculating device, a controlling device, and an eyeglass frame. The projecting light source projects assistant information via beam splitter. The image sensor captures an eye image. The calculating device calculates an object distance and a viewing direction according to the eye image. The controlling device according to the object distance controls the projecting light source to adjust an image location of the assistant information, and controls the projecting light source to adjust a projecting light angle and an angle of the beam splitter according to the viewing direction. The eyeglass frame carries the projecting light source, the beam splitter, the image sensor, the calculating device and the controlling device.
    Type: Application
    Filed: October 29, 2013
    Publication date: February 5, 2015
    Applicant: QUANTA COMPUTER INC.
    Inventors: Chung-Te LI, Wen-Chu YANG, Chih-Chi CHENG