Patents by Inventor Chih-Chi Wang

Chih-Chi Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9686336
    Abstract: A communicating apparatus comprising a receiving module which comprises: a first receiving line, for receiving a second input data stream; a timing detecting apparatus, for detecting timings for a plurality of data units of the second input data stream; a data allocating apparatus, for allocating the second input data stream to X allocated data streams, wherein the X is a positive integer and the X is larger or equals to 2; and X second receiving lines, for respectively transmitting one of the X allocated data streams.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: June 20, 2017
    Assignee: Realtek Semiconductor Corp.
    Inventors: Heng Cheong Lao, Ta-Chin Tseng, Chih-Chi Wang, Liang-Wei Huang
  • Publication number: 20150016474
    Abstract: A communicating apparatus comprising a receiving module which comprises: a first receiving line, for receiving a second input data stream; a timing detecting apparatus, for detecting timings for a plurality of data units of the second input data stream; a data allocating apparatus, for allocating the second input data stream to X allocated data streams, wherein the X is a positive integer and the X is larger or equals to 2; and X second receiving lines, for respectively transmitting one of the X allocated data streams.
    Type: Application
    Filed: July 7, 2014
    Publication date: January 15, 2015
    Inventors: HENG CHEONG LAO, Ta-Chin Tseng, Chih-Chi Wang, Liang-Wei Huang
  • Patent number: 8718273
    Abstract: An echo signal processing apparatus is disclosed. The echo signal processing apparatus is utilized for generating a cancellation signal by using group phenomenon of a frequency response of an echo signal to remove the echo signal. The echo signal processing apparatus has lower cost and is able to remove the echo efficiently.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: May 6, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chih-Chi Wang, Rong-Jen Chang, Ting-Fa Yu, Li-Wei Fang
  • Patent number: 8537728
    Abstract: A communication apparatus with echo cancellation includes a transmitter, a receiver, a digital echo cancellation circuit, a parameter control circuit, and an analog echo cancellation circuit. The digital echo cancellation circuit determines an echo estimation component according to a digital output signal, and performs a digital echo cancellation on a digital input signal according to the echo estimation component. The parameter control circuit generates a control signal according to the echo estimation component. The analog echo cancellation circuit includes a first echo cancellation resistor and a second echo cancellation resistor, wherein the resistances of the first echo cancellation resistor and the second echo cancellation resistor are adjusted according to the control signal.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: September 17, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventors: Liang-Wei Huang, Ting-Fa Yu, Ta-Chin Tseng, Chih-Chi Wang
  • Publication number: 20100208577
    Abstract: A communication apparatus with echo cancellation includes a transmitter, a receiver, a digital echo cancellation circuit, a parameter control circuit, and an analog echo cancellation circuit. The digital echo cancellation circuit determines an echo estimation component according to a digital output signal, and performs a digital echo cancellation on a digital input signal according to the echo estimation component. The parameter control circuit generates a control signal according to the echo estimation component. The analog echo cancellation circuit includes a first echo cancellation resistor and a second echo cancellation resistor, wherein the resistances of the first echo cancellation resistor and the second echo cancellation resistor are adjusted according to the control signal.
    Type: Application
    Filed: February 9, 2010
    Publication date: August 19, 2010
    Inventors: Liang-Wei Huang, Ting-Fa Yu, Ta-Chin Tseng, Chih-Chi Wang
  • Publication number: 20100208882
    Abstract: An echo signal processing apparatus is disclosed. The echo signal processing apparatus is utilized for generating a cancellation signal by using group phenomenon of a frequency response of an echo signal to remove the echo signal. The echo signal processing apparatus has lower cost and is able to remove the echo efficiently.
    Type: Application
    Filed: January 14, 2010
    Publication date: August 19, 2010
    Inventors: Chih-Chi Wang, Rong-Jen Chang, Ting-Fa Yu, Li-Wei Fang
  • Patent number: 7760749
    Abstract: The invention provides an Ethernet physical layer (PHY) receiver. Ethernet PHY signals are simultaneously transmitted through first, second, third, and fourth duplex channels. The Ethernet physical layer receiver comprises a deskew first-in first-out (FIFO) module and a deskew control module. The deskew FIFO module includes four deskew FIFO buffers for respectively holding the Ethernet PHY signals of the duplex channels, wherein the Ethernet PHY signals of the duplex channels are respectively retrieved from the deskew FIFO buffers for further processing through read points of the deskew FIFO buffers.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: July 20, 2010
    Assignee: Via Technologies, Inc.
    Inventors: Chih-Chi Wang, Yi-Hua Lai
  • Publication number: 20080170582
    Abstract: The invention provides an Ethernet physical layer (PHY) receiver. Ethernet PHY signals are simultaneously transmitted through first, second, third, and fourth duplex channels. The Ethernet physical layer receiver comprises a deskew first-in first-out (FIFO) module and a deskew control module. The deskew FIFO module includes four deskew FIFO buffers for respectively holding the Ethernet PHY signals of the duplex channels, wherein the Ethernet PHY signals of the duplex channels are respectively retrieved from the deskew FIFO buffers for further processing through read points of the deskew FIFO buffers.
    Type: Application
    Filed: January 11, 2007
    Publication date: July 17, 2008
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Chih-Chi Wang, Yi-Hua Lai
  • Publication number: 20030118094
    Abstract: A method for training a time-domain equalizer having at least one coefficient that includes estimating a channel, initializing the at least one coefficient of the time-domain equalizer, updating the at least one coefficient of the time-domain equalizer with the estimated channel, retaining the updated estimated channel, fixing the updated value of the at least one coefficient of the time-domain equalizer for at least a one-symbol duration, calculating a modulated symbol based on an output of the time-domain equalizer, calculating a second value for the estimated channel based on the modulated symbol, setting the estimated channel to the second value, and repeating the step of updating the time-domain equalizer through the step of setting the estimated channel to the second value until a predetermined condition has been met.
    Type: Application
    Filed: December 21, 2001
    Publication date: June 26, 2003
    Inventors: Chih-Chi Wang, An-Yeu Wu, Bor-Min Wang