Patents by Inventor Chih-Chia Chiu

Chih-Chia Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11982866
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 14, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Patent number: 11979593
    Abstract: Method and apparatus for affine CPMV or ALF refinement are mentioned. According to this method, statistical data associated with the affine CPMV or ALF refinement are collected over a picture area. Updated parameters for the affine CPMV refinement or the ALF refinement are then derived based on the statistical data, where a process to derive the updated parameters includes performing multiplication using a reduced-precision multiplier for the statistical data. The reduced-precision multiplier truncates at least one bit of the mantissa part. In another embodiment, the process to derive the updated parameters includes performing reciprocal for the statistical data using a lookup table with (m?k)-bit input by truncating k bits from the m-bit mantissa part, and contents of the lookup table includes m-bit outputs. m and k are positive integers.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: May 7, 2024
    Assignee: MEDIATEK INC.
    Inventors: Shih-Chun Chiu, Tzu-Der Chuang, Ching-Yeh Chen, Chun-Chia Chen, Chih-Wei Hsu, Yu-Wen Huang
  • Patent number: 11973985
    Abstract: Various schemes pertaining to pre-encoding processing of a video stream with motion compensated temporal filtering (MCTF) are described. An apparatus determines a filtering interval for a received raw video stream having pictures in a temporal sequence. The apparatus selects from the pictures a plurality of target pictures based on the filtering interval, as well as a group of reference pictures for each target picture to perform pixel-based MCTF, which generates a corresponding filtered picture for each target picture. The apparatus subsequently transmits the filtered pictures as well as non-target pictures to an encoder for encoding the video stream. Subpictures of natural images and screen content images are separately processed by the apparatus.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: April 30, 2024
    Assignee: MediaTek Inc.
    Inventors: Chih-Yao Chiu, Chun-Chia Chen, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Publication number: 20190096444
    Abstract: A circuit for a memory system including a plurality of memories, including: a plurality of connection traces coupled in series, each connection trace having a first end, and a second end coupled to a terminal of a memory of the plurality of memories; wherein an equivalent impedance of a first connection trace of the plurality of connection traces is different with the equivalent impedance of the second connection trace of the plurality of connection traces, the first connection trace being coupled to the second connection trace in series.
    Type: Application
    Filed: September 25, 2017
    Publication date: March 28, 2019
    Inventors: Chih-Chia Chiu, Ruey-Beei Wu, Ting-Ying Wu, Wen-Shan Wang, GERCHIH CHOU
  • Patent number: D1027182
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: May 14, 2024
    Assignees: Interface Technology (ChengDu) Co., Ltd., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventors: Chun-Ming Cheng, Chih-Lin Liao, Yi-Chia Chiu, Chun-Ta Chen, Po-Lun Chen