Abstract: A lateral diffused metal oxide semiconductor (LDMOS) transistor and a manufacturing method thereof are provided. A deep well region is disposed in a substrate. An isolation structure is disposed in the substrate to define a first active area and a second active area. A well region is disposed in the deep well region in the first active area. A gate is disposed on the substrate in the first active area. A gate dielectric layer is disposed between the gate and the substrate. A first doped region is disposed in the well region in the first active area and located at one side of the gate. A second doped region is disposed in the deep well region in the second active area. A conductive structure is disposed on the isolation structure, surrounds the second doped region and is connected to the gate.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first well, a first heavily doping region, a field oxide, a first dielectric layer, and a conductive layer. The first well is disposed on the substrate, and the first heavily doping region is disposed in the first well. The field oxide is disposed on the first well and adjacent to the first heavily doping region. The first dielectric layer is disposed on the field oxide and covering the field oxide. The conductive layer is disposed on the first dielectric layer. The first well and the first heavily doping region have a first type doping.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first well, a first heavily doping region, a field oxide, a first dielectric layer, and a conductive layer. The first well is disposed on the substrate, and the first heavily doping region is disposed in the first well. The field oxide is disposed on the first well and adjacent to the first heavily doping region. The first dielectric layer is disposed on the field oxide and covering the field oxide. The conductive layer is disposed on the first dielectric layer. The first well and the first heavily doping region have a first type doping.

Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.

Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.

Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.

Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.

Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.

Abstract: A semiconductor structure and a manufacturing process thereof are disclosed. The semiconductor structure includes a substrate having a first conductive type, a first well having a second conductive type formed in the substrate, a doped region having the second conductive type formed in the first well, a field oxide and a second well having the first conductive type. The doped region has a first net dopant concentration. The field oxide is formed on a surface area of the first well. The second well is disposed underneath the field oxide and connected to a side of the doped region. The second well has a second net dopant concentration smaller than the first net dopant concentration.

Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.

Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.

Abstract: A manufacturing method for a high voltage transistor includes the following steps. A substrate is provided. A P-type epitaxial (P-epi) layer is provided above the substrate. An N-well is formed in the P-epi layer. A P-well is formed in the P-epi layer. Field oxide (FOX) layers are formed above the P-epi layer. A gate oxide (GOX) layer is formed between the FOX layers. P-type implants are doped into the P-well or N-type implants are doped into the N-well to adjust an electrical function of the high voltage transistor.

Abstract: A semiconductor structure and a manufacturing process thereof are disclosed. The semiconductor structure includes a substrate having a first conductive type, a first well having a second conductive type formed in the substrate, a doped region having the second conductive type formed in the first well, a field oxide and a second well having the first conductive type. The doped region has a first net dopant concentration. The field oxide is formed on a surface area of the first well. The second well is disposed underneath the field oxide and connected to a side of the doped region. The second well has a second net dopant concentration smaller than the first net dopant concentration.

Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.

Abstract: A manufacturing method for a high voltage transistor includes the following steps. A substrate is provided. A P-type epitaxial (P-epi) layer is provided above the substrate. An N-well is formed in the P-epi layer. A P-well is formed in the P-epi layer. Field oxide (FOX) layers are formed above the P-epi layer. A gate oxide (GOX) layer is formed between the FOX layers. P-type implants are doped into the P-well or N-type implants are doped into the N-well to adjust an electrical function of the high voltage transistor.

Abstract: A manufacturing method for a high voltage transistor includes the following steps. A substrate is provided. A P-type epitaxial (P-epi) layer is provided above the substrate. An N-well is formed in the P-epi layer. A P-well is formed in the P-epi layer. Field oxide (FOX) layers are formed above the P-epi layer. A gate oxide (GOX) layer is formed between the FOX layers. P-type implants are doped into the P-well or N-type implants are doped into the N-well to adjust an electrical function of the high voltage transistor.

Abstract: A temporal protection layer is employed to a wafer backside for use of micro-electro-mechanical systems (MEMS). The formation of the temporal protection layer prevents the wafer backside from scratch in process of transferring system for IC manufacturers. With regard to low cost and easy forming and removing, an oxide layer is used as the temporal protection layer. The throughput and yield rate of the wafer production are improved by the use of the temporal protection layer.

Abstract: A temporal protecting layer is employed to a wafer backside for use of micro-electro-mechanical systems (MEMS). The formation of the temporal protecting layer prevents the wafer backside from scratch in process of transferring system for IC manufacturers. In concerning with low cost and easily forming and removing, an oxide layer is used as the temporal protecting layer. The throughput and yield rate for the wafer are improved by the temporal protecting layer.

Abstract: A method for monitoring overlay alignment on a wafer that includes identifying a target machine, identifying a target process, identifying a plurality of critical layers, obtaining a plurality of overlay data from at least one of designated registration patterns on the wafer as baseline data, providing a plurality of reference overlay data, correlating the plurality of the reference overlay data with the baseline data to obtain overlay error, comparing the overlay error with specifications of the target machine, accepting the baseline data when the overlay error is within the specifications, and performing overlay alignment monitoring with the baseline data.

Abstract: A method for monitoring overlay alignment on a wafer that includes identifying a target machine, identifying a target process, identifying a plurality of critical layers, obtaining a plurality of overlay data from at least one of designated registration patterns on the wafer as baseline data, providing a plurality of reference overlay data, correlating the plurality of the reference overlay data with the baseline data to obtain overlay error, comparing the overlay error with specifications of the target machine, accepting the baseline data when the overlay error is within the specifications, and performing overlay alignment monitoring with the baseline data.