Patents by Inventor Chih-Chia Hu
Chih-Chia Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11676908Abstract: A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.Type: GrantFiled: December 16, 2019Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chia Hu, Chang-Ching Yu, Ming-Fa Chen
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Publication number: 20230154810Abstract: A semiconductor package includes a first die. The first die has a first side and a second side different from the first side and includes a first seal ring. The first seal ring includes a first portion at the first side and a second portion at the second side, and a width of the first portion is smaller than a width of the second portion.Type: ApplicationFiled: January 17, 2023Publication date: May 18, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Chih-Chia Hu
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Publication number: 20230139919Abstract: Seamless bonding layers in semiconductor packages and methods of forming the same are disclosed. In an embodiment, a method includes forming a second passivation layer over a first metal pad and a second metal pad, the first metal pad and the second metal pad being disposed over a first passivation layer of a first semiconductor die; depositing a first bonding material over the second passivation layer to form a first portion of a first bonding layer, wherein at least a portion of a seam in the first bonding layer is between the first metal pad and the second metal pad; thinning the first portion of the first bonding layer to create a first opening from the seam; and re-depositing the first bonding material to fill the first opening and to form a second portion of the first bonding layer.Type: ApplicationFiled: January 21, 2022Publication date: May 4, 2023Inventors: Chih-Chia Hu, Ming-Fa Chen
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Publication number: 20230113285Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.Type: ApplicationFiled: December 15, 2022Publication date: April 13, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chia Hu, Ming-Fa Chen, Sung-Feng Yeh
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Publication number: 20230095134Abstract: Embodiments utilize a bridge die that directly bonds to and bridges two or more device dies. Each of the device dies can have additional device dies stacked thereupon. In some embodiments, the bridge die can bridge device dies disposed both under and over the bridge die. In some embodiments, several bridge dies may be used to bridge a device die to other adjacent device dies.Type: ApplicationFiled: March 18, 2022Publication date: March 30, 2023Inventors: Ming-Fa Chen, Min-Chien Hsiao, Chih-Chia Hu, Han-Ping Pu, Ching-Yu Huang, Chen-Sheng Lin, Sung-Feng Yeh, Chao-Wen Shih
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Patent number: 11574847Abstract: A forming method of a semiconductor package includes the following steps. A first die is provided. The first die includes a first bonding structure and a first seal ring, the first bonding structure is formed at a first side of the first die, a first portion of the first seal ring is formed between the first side and the first bonding structure, and a width of the first portion is smaller than a width of a second portion of the first seal ring. A second die is provided. The second die includes a second bonding structure. The first die and the second die are bonded onto an integrated circuit through the first bonding structure and the second bonding structure.Type: GrantFiled: July 27, 2021Date of Patent: February 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Chih-Chia Hu
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Patent number: 11562982Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.Type: GrantFiled: April 29, 2019Date of Patent: January 24, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chia Hu, Ming-Fa Chen, Sung-Feng Yeh
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Publication number: 20220375878Abstract: A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.Type: ApplicationFiled: August 5, 2022Publication date: November 24, 2022Inventors: Chih-Chia Hu, Chun-Chiang Kuo, Sen-Bor Jan, Ming-Fa Chen, Hsien-Wei Chen
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Publication number: 20220367322Abstract: A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Inventors: Chih-Chia Hu, Sen-Bor Jan, Hsien-Wei Chen, Ming-Fa Chen
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Publication number: 20220357652Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.Type: ApplicationFiled: July 27, 2022Publication date: November 10, 2022Inventors: Peter Yu, Chih-Tung Hsu, Kevin Wang, Chih-Chia Hu, Roger Chen
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Publication number: 20220359462Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chia Hu, Ming-Fa Chen, Sung-Feng Yeh
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Patent number: 11482499Abstract: A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.Type: GrantFiled: August 10, 2020Date of Patent: October 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chia Hu, Chun-Chiang Kuo, Sen-Bor Jan, Ming-Fa Chen, Hsien-Wei Chen
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Patent number: 11462458Abstract: A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.Type: GrantFiled: February 22, 2021Date of Patent: October 4, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chia Hu, Sen-Bor Jan, Hsien-Wei Chen, Ming-Fa Chen
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Publication number: 20220278063Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.Type: ApplicationFiled: May 16, 2022Publication date: September 1, 2022Inventors: Chih-Chia Hu, Ching-Pin Yuan, Sung-Feng Yeh, Sen-Bor Jan, Ming-Fa Chen
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Publication number: 20220262766Abstract: A method includes bonding a tier-1 device die to a carrier, forming a first gap-filling region to encapsulate the tier-1 device die, forming a first redistribution structure over and electrically connected to the tier-1 device die, and bonding a tier-2 device die to the tier-1 device die. The tier-2 device die is over the tier-1 device die, and the tier-2 device die extends laterally beyond a corresponding edge of the tier-1 device die. The method further includes forming a second gap-filling region to encapsulate the tier-2 device die, removing the carrier, and forming a through-dielectric via penetrating through the first gap-filling region. The through-dielectric via is overlapped by, and is electrically connected to, the tier-2 device die. A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are on opposing sides of the tier-1 device die.Type: ApplicationFiled: April 13, 2021Publication date: August 18, 2022Inventors: Ming-Fa Chen, Chuan-An Cheng, Sung-Feng Yeh, Chih-Chia Hu
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Patent number: 11402747Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.Type: GrantFiled: May 3, 2021Date of Patent: August 2, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Peter Yu, Chih-Tung Hsu, Kevin Wang, Chih-Chia Hu, Roger Chen
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Patent number: 11335656Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.Type: GrantFiled: September 21, 2020Date of Patent: May 17, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chia Hu, Ching-Pin Yuan, Sung-Feng Yeh, Sen-Bor Jan, Ming-Fa Chen
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Publication number: 20220139885Abstract: A method includes bonding a first device die with a second device die. The second device die is over the first device die. A passive device is formed in a combined structure including the first and the second device dies. The passive device includes a first and a second end. A gap-filling material is formed over the first device die, with the gap-filling material including portions on opposite sides of the second device die. The method further includes performing a planarization to reveal the second device die, with a remaining portion of the gap-filling material forming an isolation region, forming a first and a second through-vias penetrating through the isolation region to electrically couple to the first device die, and forming a first and a second electrical connectors electrically coupling to the first end and the second end of the passive device.Type: ApplicationFiled: January 17, 2022Publication date: May 5, 2022Inventors: Chih-Chia Hu, Ming-Fa Chen
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Patent number: 11239205Abstract: A method includes bonding a first device die with a second device die. The second device die is over the first device die. A passive device is formed in a combined structure including the first and the second device dies. The passive device includes a first and a second end. A gap-filling material is formed over the first device die, with the gap-filling material including portions on opposite sides of the second device die. The method further includes performing a planarization to reveal the second device die, with a remaining portion of the gap-filling material forming an isolation region, forming a first and a second through-vias penetrating through the isolation region to electrically couple to the first device die, and forming a first and a second electrical connectors electrically coupling to the first end and the second end of the passive device.Type: GrantFiled: January 13, 2020Date of Patent: February 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chia Hu, Ming-Fa Chen
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Publication number: 20220012402Abstract: A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.Type: ApplicationFiled: July 1, 2021Publication date: January 13, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chia Hu, Ming-Fa Chen, Sen-Bor Jan, Meng-Wei Chiang