Patents by Inventor Chih-Chiang Chen

Chih-Chiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11901258
    Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
  • Publication number: 20240036738
    Abstract: A method for performing link management of a memory device in predetermined communications architecture with aid of handshaking phase transition control and associated apparatus are provided. The method may include: utilizing at least one upper layer controller of a transmission interface circuit to turn on a physical layer (PHY) circuit of the transmission interface circuit, for starting establishing a link between a host device and the memory device; before entering a first handshaking phase, utilizing the PHY circuit to receive any first incoming data sent from the host device to determine whether the any first incoming data indicates that the host device is in a corresponding first handshaking phase; and in response to the any first incoming data indicating that the host device is in the corresponding first handshaking phase, utilizing the PHY circuit to send first outgoing data that is equal to first predetermined data to the host device.
    Type: Application
    Filed: July 26, 2022
    Publication date: February 1, 2024
    Applicant: Silicon Motion, Inc.
    Inventors: Bo-Chang Ye, Kuo-Cyuan Kuo, Chih-Chiang Chen
  • Publication number: 20240019620
    Abstract: A display device includes a first image generating unit and a first waveguide glass. The first image generating unit is configured to emit first light. The first waveguide glass faces toward the first image generating unit. The first waveguide glass includes a first microstructure, two second microstructures and a third microstructure. The first microstructure is located between two ends at the same side of the two second microstructures. The third microstructure is located between the two second microstructures. The third microstructure has a first grating and a second grating. An extending direction of the first grating is different from an extending direction of the second grating. The second microstructure is configured to receive the first light of the first image generating unit transmitted through the first microstructure and transmit the first light to the third microstructure.
    Type: Application
    Filed: November 30, 2022
    Publication date: January 18, 2024
    Inventors: Han-Sheng NIAN, Ming-Jui WANG, Chih-Chiang CHEN, Chia-Hsin CHUNG, Yu-Cheng SHIH, Wei-Syun WANG, Cheng-Chan WANG, Hsin-Hung LI, Sheng-Ming HUANG
  • Publication number: 20240021544
    Abstract: A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 18, 2024
    Inventors: Chih-Chia Hu, Chun-Chiang Kuo, Sen-Bor Jan, Ming-Fa Chen, Hsien-Wei Chen
  • Publication number: 20240018149
    Abstract: This disclosure relates to bivalent compounds (e.g., bi-functional small molecule compounds), compositions comprising one or more of the bivalent compounds, and to methods of use the bivalent compounds for the degrading target proteins associated with a disease or condition.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 18, 2024
    Inventors: Chu-Chiang LIN, Hung-Chuan CHEN, Pei-Chin Xizhou, Chih-Chang CHOU
  • Patent number: 11874513
    Abstract: In an embodiment, a package structure including an electro-optical circuit board, a fanout package disposed over the electro-optical circuit board is provided. The electro-optical circuit board includes an optical waveguide. The fanout package includes a first optical input/output portion, a second optical input/output portion and a plurality of electrical input/output terminals electrically connected to the electro-optical circuit board. The first optical input/output portion is optically coupled to the second optical input/output portion through the optical waveguide of the electro-optical circuit board.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: January 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lun Chang, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hsuan-Ting Kuo, Chia-Shen Cheng, Chih-Chiang Tsao
  • Publication number: 20240012241
    Abstract: A head-up display includes an image generating unit and a waveguide glass. The waveguide glass faces toward the image generating unit. The waveguide glass includes a first microstructure, a second microstructure and a third microstructure. The first microstructure has a first width. The second microstructure is adjacent to the first microstructure. The third microstructure is adjacent to the second microstructure. The third microstructure has tiling areas adjacent to each other. A gap between the two adjacent tiling areas is less than half of the first width.
    Type: Application
    Filed: November 29, 2022
    Publication date: January 11, 2024
    Inventors: Han-Sheng NIAN, Seok-Lyul LEE, Ming-Jui WANG, Chih-Chiang CHEN, Chia-Hsin CHUNG, Yu-Cheng SHIH, Cheng-Chan WANG, Hsin-Hung LI, Wei-Syun WANG, Sheng-Ming HUANG
  • Patent number: 11869816
    Abstract: A package substrate comprises first, second and third electrical test contacts, wherein the package substrate is provided with an upper element plane and a lower SMD electrode plane on two sides. The side edge of the upper element plane is provided with first and second electrodes of the main element and first and second electrodes of the secondary element. The main element of LED chip is electrically connected between the first and second electrodes of the main element, a parallel circuit secondary element is electrically connected between the first and second electrodes of the secondary element. The electrical characteristics of the main element of LED chip and the parallel circuit secondary element are measured through the first, second, and third electrical test contacts when electrically connected.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: January 9, 2024
    Assignee: EXCELLENCE OPTO. INC.
    Inventors: Fu-Bang Chen, Chih-Chiang Chang, Chang-Ching Huang, Chun-Ming Lai, Wen-Hsing Huang, Tzeng-Guang Tsai, Kuo-Hsin Huang
  • Patent number: 11866632
    Abstract: Liquid-crystal polymer is composed of the following repeating units: 10 mol % to 35 mol % of 10 mol % to 35 mol % of 10 mol % to 50 mol % of and 10 mol % to 40 mol % of 10 mol % to 40 mol % of or a combination thereof. Each of AR1, AR2, AR3, and AR4 is independently AR5 or AR5-Z-AR6, in which each of AR5 and AR6 is independently or a combination thereof, and Z is —O—, or C1-5 alkylene group. Each of X and Y is independently H, C1-5 alkyl group, CF3, or wherein R2 is H, CH3, CH(CH3)2, C(CH3)3, CF3, or n=1 to 4; and wherein R1 is C1-5 alkylene group.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: January 9, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Lin Chu, Jen-Chun Chiu, Zu-Chiang Gu, Po-Hsien Ho, Meng-Hsin Chen, Chih-Hsiang Lin
  • Patent number: 11869817
    Abstract: The invention comprises a light emitting diode chip and a package substrate. The light emitting diode chip is provided with a semiconductor epitaxial structure, a lateral extending interface structure, a chip conductive structure, an N-type electrode located above the semiconductor epitaxial structure and a P-type bypass detection electrode located on the lateral extending interface structure. The chip conductive structure is provided with a P-type main electrode located on a lower side. The package substrate comprises a plurality of electrode contacts through which the N-type electrode, the P-type bypass detection electrode and the P-type main electrode are connected, and a process quality of a alternative substrate adhesive layer in one of the semiconductor epitaxial structure and the chip conductive structure and a chip-substrate bonding adhesive layer between the P-type main electrode and the package substrate is evaluated by detecting electrical characteristics.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: January 9, 2024
    Assignee: EXCELLENCE OPTO. INC.
    Inventors: Fu-Bang Chen, Chih-Chiang Chang, Chang-Ching Huang, Chun-Ming Lai, Wen-Hsing Huang, Tzeng-Guang Tsai, Kuo-Hsin Huang
  • Publication number: 20240003827
    Abstract: In a mask review method, a vacuum is drawn in a vacuum chamber that contains an extreme ultraviolet (EUV) actinic mask review system including an EUV illuminator, a mask stage, a projection optics box, and an EUV imaging sensor. With the vacuum drawn, a position is adjusted of at least one component of the EUV actinic mask review system. After the adjusting and with the vacuum drawn, an actinic image is acquired of an EUV mask mounted on the mask stage using the EUV imaging sensor. The acquiring includes transmitting EUV light from the EUV illuminator onto the EUV mask and projecting at least a portion of the EUV light reflected by the EUV mask onto the EUV imaging sensor using the projection optics box.
    Type: Application
    Filed: January 4, 2023
    Publication date: January 4, 2024
    Inventors: Chien-Lin Chen, Danping Peng, Chih-Chiang Tu, Chih-Wei Wen, Hsin-Fu Tseng
  • Patent number: 11862577
    Abstract: Provided is a package structure, including a die, a plurality of through vias, an encapsulant, a plurality of first connectors, a warpage control material and a protection material. The plurality of through vias are disposed around the die. The encapsulant laterally encapsulate the die and the plurality of through vias. The plurality of first connectors are electrically connected to a first surface of the plurality of through vias. The warpage control material is disposed over a first surface of the die. The protection material is disposed over the encapsulant, around the plurality of first connectors and the warpage control material. A Young's modulus of the warpage control material is greater than a Young's modulus of the encapsulant, and the Young's modulus of the encapsulant is greater than a Young's modulus of the protection material.
    Type: Grant
    Filed: December 24, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
  • Patent number: 11860530
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Patent number: 11854861
    Abstract: A spin dry etching process includes loading an object into a dry etching system. A dry etching process is performed to the object, and the object is spun while the dry etching process is being performed. The spin dry etching process is performed using a semiconductor fabrication system. The semiconductor fabrication system includes a dry etching chamber in which a dry etching process is performed. A holder apparatus has a horizontally-facing slot that is configured for horizontal insertion of an etchable object therein. The etchable object includes either a photomask or a wafer. A controller is communicatively coupled to the holder apparatus and configured to spin the holder apparatus in a clockwise or counterclockwise direction while the dry etching process is being performed. An insertion of the etchable object into the horizontally-facing slot of the holder apparatus restricts a movement of the object as the dry etching process is performed.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen
  • Patent number: 11842862
    Abstract: A keyboard device with a display panel including a base, a scissors feet assembly movably disposed on the base, an elastic member disposed on the base, a display panel supported by the scissors feet assembly and the elastic member, and multiple light transmittance keycaps disposed on the display panel is provided. The display panel has multiple display surfaces, multiple hollow portions, and multiple elastic portions. Each of the display surfaces is surrounded by the hollow portions, and is suspended between the hollow portions by the elastic portions. The light transmittance keycaps respectively and correspondingly cover the display surfaces.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: December 12, 2023
    Assignee: Acer Incorporated
    Inventors: Hung-Chi Chen, Kung-Cheng Lin, Chih-Chiang Chen
  • Patent number: 11837584
    Abstract: A manufacturing method of a display device is provided. The manufacturing method of the display device includes forming a switching structure. The switching structure includes a plurality of switching elements. The manufacturing method of the display device also includes forming a light-emitting structure. The light-emitting structure includes a plurality of light-emitting elements. The manufacturing method of the display device further includes arranging the light-emitting structure on the switching structure, so that each of the light-emitting elements is above each of the switching elements. The manufacturing method of the display device includes connecting each of the light-emitting elements to a corresponding switching element via a laser.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: December 5, 2023
    Assignee: ACER INCORPORATED
    Inventors: Jui-Chieh Hsiang, Chih-Chiang Chen
  • Patent number: 11836893
    Abstract: A video processing circuit includes an input buffer, an online adaptation circuit, and an artificial intelligence (AI) super-resolution (SR) circuit. The input buffer receives input low-resolution (LR) frames and high-resolution (HR) frames from a video source over a network. The online adaptation circuit forms training pairs, and calculates an update to representative features that characterize the input LR frames using the training pairs. Each training pair formed by one of the input LR frames and one of the HR frames. The AI SR circuit receives the input LR frames from the input buffer and the representative features from the online adaptation circuit. Concurrently with calculating the update to the representative features, the AI SR circuit generates SR frames for display from the input LR frames based on the representative features. Each SR frame has a higher resolution than a corresponding one of the input LR frames.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: December 5, 2023
    Assignee: MediaTek Inc.
    Inventors: Cheng Lung Jen, Pei-Kuei Tsung, Yao-Sheng Wang, Chih-Wei Chen, Chih-Wen Goo, Yu-Cheng Tseng, Ming-En Shih, Kuo-Chiang Lo
  • Patent number: 11837663
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A first gate spacer is formed adjacent to a sidewall of the conductive gate stack. A source/drain contact structure is formed adjacent to the first gate spacer. An insulating capping layer covers and is in direct contact with an upper surface of the conductive gate stack. A top width of the insulating capping layer is substantially equal to a top width of the conductive gate stack. The insulating capping layer is separated from the source/drain contact structure by the first gate spacer.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Chih-Hong Hwang, Jyh-Huei Chen
  • Publication number: 20230386926
    Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.
    Type: Application
    Filed: August 2, 2023
    Publication date: November 30, 2023
    Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
  • Publication number: 20230386862
    Abstract: A method includes forming regions of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming solder bumps on an interconnect structure, wherein the solder bumps have a second melting temperature that is greater than the first melting temperature; placing the solder bumps on the regions of solder paste; performing a first reflow process at a first reflow temperature for a first duration of time, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration of time, wherein the second reflow temperature is greater than the second melting temperature.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Wei-Yu Chen, Hao-Jan Pei, Hsuan-Ting Kuo, Chih-Chiang Tsao, Jen-Jui Yu, Philip Yu-Shuan Chung, Chia-Lun Chang, Hsiu-Jen Lin, Ching-Hua Hsieh