Patents by Inventor Chih-Chiang Chen
Chih-Chiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12266559Abstract: A method of handling a workpiece includes the following steps. A workpiece is placed on a chuck body, wherein the workpiece includes a tape carrier extending beyond a periphery of the chuck body and a workpiece body disposed on the tape carrier, and the chuck body includes a seal ring surrounding the periphery of the chuck body; the tape carrier is clamped outside the chuck body, wherein the tape carrier leans against the seal ring and an enclosed space is formed between the chuck body, the tape carrier and the seal ring; and a vacuum seal is formed by evacuating gas from the enclosed space to pull the periphery of the workpiece toward the chuck body.Type: GrantFiled: July 26, 2023Date of Patent: April 1, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Shiuan Wong, Chih-Chiang Tsao, Chao-Wei Chiu, Hao-Jan Pei, Wei-Yu Chen, Hsiu-Jen Lin, Ching-Hua Hsieh, Chia-Shen Cheng
-
Publication number: 20250105163Abstract: A semiconductor chiplet device includes a first die, a second die, a decoupling circuit and an interposer. The interposer includes a plurality of power traces and a plurality of ground traces. The first die and the second die are arranged on a first side of the interposer according to a configuration direction, and are coupled to the power traces and the ground traces. The decoupling circuit is arranged on a second side of the interposer, and is coupled to the power traces and the ground traces. The power traces and the ground traces are staggered with each other, and an extending direction of the ground traces and the power traces is the same as the configuration direction.Type: ApplicationFiled: March 20, 2024Publication date: March 27, 2025Inventors: Liang-Kai CHEN, Chih-Chiang HUNG, Wen-Yi JIAN, Yuan-Hung LIN, Sheng-Fan YANG
-
Patent number: 12262479Abstract: The present invention relates to an extension structure of flexible substrates with conductive wires thereon. In a first embodiment, three flexible substrates are prepared, each having multiple conductive wires configured on their front surfaces. The third flexible substrate is flipped over, with its conductive wires facing downwards, and bonded across a boundary formed by the first and second flexible substrates. As a result, the corresponding conductive wires between the first and second flexible substrates are electrically coupled with each other through being physically pressed by corresponding conductive wires in the third flexible substrate.Type: GrantFiled: March 16, 2023Date of Patent: March 25, 2025Assignee: UNEO INC.Inventors: Chih-Sheng Hou, Chia-Hung Chou, Hsin-Lin Yu, Si-Wei Chen, Chueh Chiang
-
Patent number: 12261088Abstract: A package structure includes a die, an encapsulation layer, a redistribution layer structure and an adhesive material. The die includes a semiconductor substrate, conductive pads disposed over the semiconductor substrate and a passivation layer disposed over the semiconductor substrate and around the conductive pads. The encapsulation layer laterally encapsulates the die. the redistribution layer structure is disposed on the die and the encapsulation layer, and includes at least one redistribution layer embedded in at least one polymer layer, and the polymer layer contacts a portion of the passivation layer. The adhesive material is disposed on the die and covers an interface between the polymer layer and the passivation layer.Type: GrantFiled: August 31, 2021Date of Patent: March 25, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Jui Yu, Hao-Jan Pei, Cheng-Ting Chen, Chih-Chiang Tsao, Hsiu-Jen Lin, Ching-Hua Hsieh
-
Patent number: 12253776Abstract: A method of forming an electronic device including: providing an assembly, wherein the assembly includes a substrate, an optical film, a plurality of color filters and a defect, wherein the plurality of color filters and the defect are disposed between the substrate and the optical film; and using a laser pulse to form a first processed area that corresponds to the defect in the optical film, wherein the first processed area at least partially overlaps at least two of the plurality of color filters.Type: GrantFiled: March 25, 2024Date of Patent: March 18, 2025Assignee: INNOLUX CORPORATIONInventors: Tai-Chi Pan, Chin-Lung Ting, I-Chang Liang, Chih-Chiang Chang Chien, Po-Wen Lin, Kuang-Ming Fan, Sheng-Nan Chen
-
Patent number: 12255104Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.Type: GrantFiled: August 2, 2023Date of Patent: March 18, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
-
Publication number: 20250081529Abstract: Embodiments with present disclosure provides a gate-all-around FET device including extended bottom inner spacers. The extended bottom inner prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.Type: ApplicationFiled: March 1, 2024Publication date: March 6, 2025Inventors: Chien-Chia CHENG, Chih-Chiang CHANG, Ming-Hua YU, Chii-Horng LI, Chung-Ting KO, Sung-En LIN, Chih-Shan CHEN, De-Fang CHEN
-
Patent number: 12237394Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.Type: GrantFiled: July 26, 2023Date of Patent: February 25, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
-
Patent number: 12230597Abstract: A package structure is provided. The package structure includes a semiconductor chip and a protective layer laterally surrounding the semiconductor chip. The package structure also includes a polymer-containing element over the protective layer. The protective layer is wider than the polymer-containing element.Type: GrantFiled: June 16, 2023Date of Patent: February 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Chih-Chiang Tsao, Wei-Yu Chen, Hsiu-Jen Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
-
Publication number: 20250056712Abstract: A manufacturing method of the circuit board includes the following. The third substrate has an opening and includes a first, a second and a third dielectric layers. The opening penetrates the first and the second dielectric layers, and the opening is fully filled with the third dielectric layer. The first, the second and the third substrates are press-fitted so that the second substrate is located between the first and the third substrates. Multiple conductive structures are formed so that the first, the second and the third substrates are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, and the third dielectric layer of the third substrate. The conductive via structure is electrically connected to the first and the third substrates to define a signal path. The ground path surrounds the signal path.Type: ApplicationFiled: October 29, 2024Publication date: February 13, 2025Applicant: Unimicron Technology Corp.Inventors: Jun-Rui Huang, Chih-Chiang Lu, Yi-Pin Lin, Ching-Sheng Chen
-
Patent number: 12218260Abstract: Disclosed are devices for optical sensing and manufacturing method thereof. In one embodiment, a device for optical sensing includes a substrate, a photodetector and a reflector. The photodetector is disposed in the substrate. The reflector is disposed in the substrate and spaced apart from the photodetector, wherein the reflector has a reflective surface inclined relative to the photodetector that reflects light transmitted thereto to the photodetector.Type: GrantFiled: July 26, 2022Date of Patent: February 4, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chiang Chang, Chia-Chan Chen
-
Patent number: 12211753Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.Type: GrantFiled: January 24, 2024Date of Patent: January 28, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sai-Hooi Yeong, Bo-Feng Young, Chi-On Chui, Chih-Chieh Yeh, Cheng-Hsien Wu, Chih-Sheng Chang, Tzu-Chiang Chen, I-Sheng Chen
-
Publication number: 20240372977Abstract: A stereoscopic display device includes a sensing device and a display device. The sensing device is suitable for sensing position information and viewing angle information of a user. The display device is connected to the sensing device and suitable for receiving the position information and the viewing angle information. The display device includes a substrate and a plurality of pixels, wherein each of the plurality of pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel having main light-emitting directions different from each other. The display device correspondingly turns on at least one of the first sub-pixel, the second sub-pixel, and the third sub-pixel and turns off at least another of the first sub-pixel, the second sub-pixel, and the third sub-pixel based on the position information and the viewing angle information.Type: ApplicationFiled: July 6, 2023Publication date: November 7, 2024Applicant: Acer IncorporatedInventors: Jui-Chieh Hsiang, Chih-Chiang Chen, Chao-Shih Huang
-
Publication number: 20240333900Abstract: Disclosed are a display device and an operating method thereof. The display device includes an eye tracking circuit, a main display, an extended display, and an image processing circuit. By the eye tracking circuit disposed in the main display, the image processing circuit obtains a viewing position of eyes of a user. The image processing circuit divides an original image into a first partial image and a second partial image. The first partial image is adapted to be displayed on the main display, and the second partial image is adapted to be virtually displayed on an extended virtual display. The image processing circuit converts any pixel position on the extended virtual display into a corresponding pixel position on the extended display based on the viewing position, so as to convert the second partial image into a converted second partial image to be displayed on the extended display.Type: ApplicationFiled: May 23, 2023Publication date: October 3, 2024Applicant: Acer IncorporatedInventors: Jui-Chieh Hsiang, Chih-Chiang Chen, Chao-Shih Huang
-
Patent number: 12102728Abstract: An electronic device with antibacterial effect detection and a portable device are provided. The electronic device includes an antibacterial housing, a light emitting unit, a light receiving unit and a processing unit. The antibacterial housing has a concave hole, which gradually shrinks from the inside to the outside. The light emitting unit is arranged under the concave hole of the antibacterial housing. The light emitting unit is used for emitting a detection light toward an inclined side wall of the concave hole. The light receiving unit is arranged under the concave hole of the antibacterial housing. The light receiving unit is used for receiving a detection light reflected from the inclined side wall of the concave hole. The processing unit is used for analyzing the antibacterial effect of the antibacterial housing according to the detection light.Type: GrantFiled: September 1, 2021Date of Patent: October 1, 2024Assignee: ACER INCORPORATEDInventors: Chueh-Pin Ko, Chih-Chiang Chen
-
Patent number: 12081130Abstract: A power delivery system includes a PD source device and a PD sink device. The PD source device is configured to detect its connection status with the PD sink device and determine whether its power supply is high-voltage operation. When determining that the PD source device is supplying high-voltage power and detecting that the PD source device is detached from the PD sink device, the PD source device is configured to provide an oscillating rapid discharging path for its output capacitor, thereby rapidly reducing its output voltage and suppressing electrical arc.Type: GrantFiled: August 12, 2022Date of Patent: September 3, 2024Assignee: ACER INCORPORATEDInventors: Tzu-Tseng Chan, Chih-Chiang Chen
-
Patent number: 12078608Abstract: A power supply device is provided. The power supply device includes a housing, a power converter, a controller, multiple humidity sensitive capacitors, and a feedback circuit. The housing has multiple joints. The controller controls the power converter to provide an output voltage. The humidity sensitive capacitors are respectively configured in the housing and adjacent to a corresponding joint of the joints. The humidity sensitive capacitors jointly provide a sensing capacitance value. The feedback circuit changes a gain value and a compensation bandwidth of the output voltage in response to the change of the sensing capacitance value. When the humidity of at least one of the joints increases, the sensing capacitance value is reduced, so that the gain value and the compensation bandwidth are reduced.Type: GrantFiled: October 3, 2022Date of Patent: September 3, 2024Assignee: Acer IncorporatedInventors: Tzu-Tseng Chan, Chih-Chiang Chen, Chuan-Jung Wang
-
Patent number: 12068119Abstract: A keyboard device with a display panel including a base, a scissors feet assembly movably disposed on the base, an elastic member disposed on the base, a display panel supported by the scissors feet assembly and the elastic member, and multiple light transmittance keycaps disposed on the display panel is provided. The display panel has multiple display surfaces, multiple hollow portions, and multiple elastic portions. Each of the display surfaces is surrounded by the hollow portions, and is suspended between the hollow portions by the elastic portions. The light transmittance keycaps respectively and correspondingly cover the display surfaces.Type: GrantFiled: October 24, 2023Date of Patent: August 20, 2024Assignee: Acer IncorporatedInventors: Hung-Chi Chen, Kung-Cheng Lin, Chih-Chiang Chen
-
Patent number: 12045108Abstract: An electronic apparatus and a load adjusting method thereof are provided. The method includes the following steps. Powering of an external power supply is detected. A self-power consumption time of the battery from a full capacity to a preset capacity is calculated and recorded when the powering of the external power supply is detected. A first average value of multiple self-power consumption times recorded within a preset period from a current time is calculated, and the first average value is compared with a second average value of the self-power consumption times of a previous preset period of the preset period. A value of a power limit for controlling the electronic apparatus to enter a load adjusting state is adjusted according to a comparison result.Type: GrantFiled: July 18, 2022Date of Patent: July 23, 2024Assignee: Acer IncorporatedInventors: Shuo-Jung Chou, Chuan-Jung Wang, Chih-Chiang Chen
-
Patent number: 12007663Abstract: A display apparatus including a display panel, a camera module, and a diffraction suppression device is provided. The display panel is provided with multiple signal lines and multiple display pixels. The signal lines and the display pixels are alternately arranged along at least one direction. The camera module has a light receiving surface facing the display panel. The light receiving surface is overlapped with the display panel. The diffraction suppression device is disposed between the display panel and the camera module, and has multiple first light-transmitting regions and multiple second light-transmitting regions alternately arranged along the at least one direction. The first light-transmitting regions are respectively overlapped with the display pixels. The second light-transmitting regions are respectively overlapped with the signal lines.Type: GrantFiled: April 19, 2023Date of Patent: June 11, 2024Assignee: Acer IncorporatedInventors: Jui-Chieh Hsiang, Chih-Chiang Chen