Abstract: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.

Abstract: A method of forming a semiconductor device and the structure of the semiconductor device are provided. The manufacturing method includes the following steps of: providing a semiconductor substrate with a front side and a back side; forming a collector layer in the back side; conducting a first Hydrogen implant process to the back side to form an N-type region and baking the N-type region with a first annealing temperature to form a field stop buffer layer; conducting a second Hydrogen implant process to the back side to form a lifetime control site and baking the lifetime control site with a second annealing temperature to form a defect layer, wherein the second annealing temperature being lower than the first annealing temperature; and forming a metal layer on the back side.

Abstract: Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.

Abstract: Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.

Abstract: Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.

Abstract: A driving method is provided for reducing power consumption of a liquid crystal display. The driving method includes steps of sequentially receiving first data and second data, determining whether the second data is the same as the first data, and controlling a data-line driving circuit not to read in driving data corresponding to the second data when the second data is the same as the first data.

Abstract: A semiconductor structure with dispersedly arranged active region trenches is provided. The semiconductor structure comprises a semiconductor substrate, an epitaxial layer, and an active region dielectric layer. The semiconductor substrate is doped with impurities of a first conductive type having a first impurity concentration. The epitaxial layer is doped with impurities of the first conductive type having a second impurity concentration and is formed on the semiconductor substrate. The epitaxial layer has a plurality of active region trenches formed therein being arranged in a dispersed manner. The active region dielectric layer covers a bottom and a sidewall of the active region trenches. Wherein, the active region trench has an opening in a tetragonal shape on a surface of the epitaxial layer, and the first impurity concentration is greater than the second impurity concentration.

Abstract: A trenched semiconductor structure comprises a semiconductor substrate, an epitaxial layer, an ion implantation layer, a termination region dielectric layer, an active region dielectric layer, and a first polysilicon layer. The epitaxial layer doped with impurities of a first conductive type is formed on the semiconductor substrate. A plurality of active region trenches and a termination region trench are formed in the epitaxial layer. The ion implantation layer is formed in the active region trenches by doping impurities of a second conductive type. The termination region dielectric layer covers the termination region trench. The active region dielectric layer covers the ion implantation region. The first polysilicon layer covers the active region dielectric layer and fills the active region trenches. The depth of the termination region trench is greater than that of the active region trenches and close to that of the depletion region under reverse breakdown.

Abstract: A trenched semiconductor structure comprises a semiconductor substrate, an epitaxial layer, an ion implantation layer, a termination region dielectric layer, an active region dielectric layer, and a first polysilicon layer. The epitaxial layer doped with impurities of a first conductive type is formed on the semiconductor substrate. A plurality of active region trenches and a termination region trench are formed in the epitaxial layer. The ion implantation layer is formed in the active region trenches by doping impurities of a second conductive type. The termination region dielectric layer covers the termination region trench. The active region dielectric layer covers the ion implantation region. The first polysilicon layer covers the active region dielectric layer and fills the active region trenches. The depth of the termination region trench is greater than that of the active region trenches and close to that of the depletion region under reverse breakdown.

Abstract: A semiconductor structure with dispersedly arranged active region trenches is provided. The semiconductor structure comprises a semiconductor substrate, an epitaxial layer, and an active region dielectric layer. The semiconductor substrate is doped with impurities of a first conductive type having a first impurity concentration. The epitaxial layer is doped with impurities of the first conductive type having a second impurity concentration and is formed on the semiconductor substrate. The epitaxial layer has a plurality of active region trenches formed therein being arranged in a dispersed manner. The active region dielectric layer covers a bottom and a sidewall of the active region trenches. Wherein, the active region trench has an opening in a tetragonal shape on a surface of the epitaxial layer, and the first impurity concentration is greater than the second impurity concentration.

Abstract: A thin film transistor array and a circuit structure thereof are provided. The circuit structure includes a patterned metal layer, a transparent conductive layer and a dielectric layer. The transparent conductive layer is formed on and contacts a top surface of the patterned metal layer. The dielectric layer overlies and contacts the patterned metal layer and the transparent conductive layer. In addition, the dielectric layer has a contact window to expose a portion of the transparent conductive layer. The transparent conductive layer on the top surface of the patterned metal layer can protect the surface layer metal against damage during fabrication of the contact window.

Abstract: A method for dynamically arranging DSP tasks. The method comprises receiving an audio bit stream, checking a remaining execution time as the DSP transforms the audio information into spectral information, simplifying the step of transforming the audio information when the DSP detects that the remaining execution time is shorter then a predetermined interval, and skipping one section of the audio information and decoding the remaining section when the execution time is less than a predetermined interval.

Abstract: A display apparatus and a method for transmitting control signals are disclosed. The display apparatus comprises comparatively a fewer number of control signal lines between the timing controller and the gate driver and/or between the timing controller and the source driver to transmit control signals. Thus, problems due to system complexity, noise and electromagnetic interference may be reduced, and the overall fabrication cost may be effectively reduced.

Abstract: A method for dynamically arranging DSP tasks. The method comprises receiving an audio bit stream, checking a remaining execution time as the DSP transforms the audio information into spectral information, simplifying the step of transforming the audio information when the DSP detects that the remaining execution time is shorter then a predetermined interval, and skipping one section of the audio information and decoding the remaining section when the execution time is less than a predetermined interval.

Abstract: A method for dynamically arranging DSP tasks. The method comprises receiving an audio bit stream, checking a remaining execution time as the DSP transforms the audio information into spectral information, simplifying the step of transforming the audio information when the DSP detects that the remaining execution time is shorter then a predetermined interval, and skipping one section of the audio information and decoding the remaining section when the execution time is less than a predetermined interval.

Abstract: A driving method is provided for reducing power consumption of a liquid crystal display. The driving method includes steps of sequentially receiving first data and second data, determining whether the second data is the same as the first data, and controlling a data-line driving circuit not to read in driving data corresponding to the second data when the second data is the same as the first data.

Abstract: A gamma reference voltage generating device, a method for generating gamma reference voltages, and a gray level voltage generating device are provided. The gray level voltage generating device includes a selection unit and a gray level voltage generator. The selection unit is adapted for receiving M first gamma reference voltages, and selecting N second gamma reference voltages from the M first gamma reference voltages and outputting the N second gamma reference voltages, wherein M and N are positive integers, and M>N. The gray level voltage generator is coupled to the selection unit, for generating a plurality of gray level voltages according to the N second gamma reference voltages. The gamma curve can be adaptively adjusted by using the present invention so as to improve the display quality.

Abstract: A method for dynamically arranging DSP tasks. The method comprises receiving an audio bit stream, checking a remaining execution time as the DSP transforms the audio information into spectral information, simplifying the step of transforming the audio information when the DSP detects that the remaining execution time is shorter then a predetermined interval, and skipping one section of the audio information and decoding the remaining section when the execution time is less than a predetermined interval.

Abstract: A panel display apparatus and a source driver including a set of first input terminals, a set of second input terminals, a set of first output terminals, a set of second output terminals, an interface module and a driving module are disclosed. The sets of the first and the second input terminals are coupled to a previous source driver and a timing controller, respectively. The sets of the first and the second output terminals are coupled to a following source driver and a display panel, respectively. The interface module selects the set of the first or the second input terminals upon a pre-setting, and connects the selected input terminals to the set of the first output terminals. The driving module generates at least a driving signal upon a signal of the selected input terminals. The driving signal is outputted to the display panel through the second output terminals.

Abstract: A display apparatus and a method for transmitting control signals are disclosed. The display apparatus comprises comparatively a fewer number of control signal lines between the timing controller and the gate driver and/or between the timing controller and the source driver to transmit control signals. Thus, problems due to system complexity, noise and electromagnetic interference may be reduced, and the overall fabrication cost may be effectively reduced.