Patents by Inventor Chih-Chiang Hsu

Chih-Chiang Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942550
    Abstract: A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chang Su, Yan-Ting Lin, Chien-Wei Lee, Bang-Ting Yan, Chih Teng Hsu, Chih-Chiang Chang, Chien-I Kuo, Chii-Horng Li, Yee-Chia Yeo
  • Publication number: 20240099030
    Abstract: A bonded assembly includes an interposer; a semiconductor die that is attached to the interposer and including a planar horizontal bottom surface and a contoured sidewall; a high bandwidth memory (HBM) die that is attached to the interposer; and a dielectric material portion contacting the semiconductor die and the interposer. The contoured sidewall includes a vertical sidewall segment and a non-horizontal, non-vertical surface segment that is adjoined to a bottom edge of the vertical sidewall segment and is adjoined to an edge of the planar horizontal bottom surface of the semiconductor die. The vertical sidewall segment and the non-horizontal, non-vertical surface segment are in contact with the dielectric material portion. The contoured sidewall may provide a variable lateral spacing from the HBM die to reduce local stress in a portion of the HBM die that is proximal to the interposer.
    Type: Application
    Filed: April 20, 2023
    Publication date: March 21, 2024
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Kuo-Chiang Ting, Chia-Hao Hsu, Hsien-Pin Hsu, Chih-Ta Shen, Shang-Yun Hou
  • Publication number: 20240098855
    Abstract: A localized heating device includes a plasma deforming portion and a heating portion. The plasma deforming portion includes an inlet end having a circular hole, an outlet end having an elongated hole with a first length and a first width, and a channel smoothly connected with the circular hole and the elongated hole. The heating portion, disposed at the outlet end, includes two control covers spaced by a slot. The elongated hole and the slot being oppositely disposed with respect to the plasma deforming portion. A plasma flow provided by a plasma producing source being to enter the channel via the circular hole, then to flow through the elongated hole, and finally to reach the slot.
    Type: Application
    Filed: December 7, 2022
    Publication date: March 21, 2024
    Inventors: JUI-MEI HSU, YO-SUNG LEE, YI-JIUN LIN, CHIH-CHIANG WENG
  • Publication number: 20160025324
    Abstract: A waterproof LED luminaire is provided, which mainly comprises a lamp holder, a light emitting diode module, a cover plate, a first side cover and a second side cover. Each of the first side cover and the second side cover has a waterproof groove provided on its inner wall surface. When both side covers are respectively assembled on both sides of the lamp holder, both the side edges of both sides of the lamp holder are fitted respectively with the waterproof grooves in such a manner that liquid can be prevented from infiltrating into the interior of the lamp holder. Therefore, the overall waterproof performance of the present invention can be enhanced.
    Type: Application
    Filed: July 22, 2014
    Publication date: January 28, 2016
    Inventors: Chou Jung HUANG, Chih Chiang HSU
  • Patent number: 9147375
    Abstract: A display timing control circuit is capable of rapidly adjusting display timing to achieve frame synchronization. The display timing control circuit includes an output pixel clock generator, a display timing generator, and a clock adjusting unit. The output pixel clock generator generates an output pixel clock signal according to a reference clock signal and a clock divisor. The display timing generator generates a display timing signal and an output vertical reference signal having an output frame rate according to the output pixel clock signal. The clock adjusting unit adjusts the clock divisor according to the output pixel clock signal, the output vertical reference signal, and an input vertical reference signal having an input frame rate.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: September 29, 2015
    Assignee: MStar Semiconductor, Inc.
    Inventors: Jian-Kao Chen, Chih Chiang Hsu
  • Patent number: 8421361
    Abstract: A backlight control circuit and method thereof are provided to control the backlight of a backlight module so as to enhance the dynamic contrast ratio and save power. The backlight control circuit includes an average luminance detection circuit, a luminance distribution detection unit, a pulse width control circuit and a pulse width modulator. The average luminance detection circuit detects the average luminance of a frame which includes a plurality of pixels; the luminance distribution detection unit detects the pixel luminance distribution of the frame; the pulse width control circuit generates a pulse width control signal according to the average luminance and the pixel luminance distribution of the frame; and the pulse width modulator generates a pulse width modulation (PWM) signal according to the pulse width control signal, so as to control the backlight of the backlight module.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: April 16, 2013
    Assignee: MStar Semiconductor, Inc.
    Inventors: Jian-Kao Chen, Chih Chiang Hsu
  • Patent number: 8295407
    Abstract: A decoding method and apparatus capable of automatically adjusting a sampling period is provided. The decoding apparatus decodes a serial code including at least one header pulse and a plurality of data pulses. The decoding apparatus includes a detecting unit for detecting the header pulse to generate an initialization signal, a determining unit for determining a sampling period according to the initialization signal and a pulse width of one of the data pulses, and a decoding unit for decoding the data pulses according to the sampling period.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: October 23, 2012
    Assignee: MStar Semiconductor, Inc.
    Inventors: Chih Chiang Hsu, Yu-Ming Lin
  • Publication number: 20120145725
    Abstract: A method of preparing conductive ribs on a chassis includes steps as follows. A plastic case is provided with at least one elastic rib integrally formed thereon. Then, a conductive film is formed to overlay on both an inner surface of the plastic case and the surfaces of the elastic rib. A chassis with conductive ribs and a method of assembling an electric device including the same are also provided in the invention.
    Type: Application
    Filed: July 27, 2011
    Publication date: June 14, 2012
    Applicant: Quanta Computer Inc.
    Inventors: Chih-Chiang HSU, Tsung-Ju Chiang
  • Publication number: 20120026156
    Abstract: A display timing control circuit is capable of rapidly adjusting display timing to achieve frame synchronization. The display timing control circuit includes an output pixel clock generator, a display timing generator, and a clock adjusting unit. The output pixel clock generator generates an output pixel clock signal according to a reference clock signal and a clock divisor. The display timing generator generates a display timing signal and an output vertical reference signal having an output frame rate according to the output pixel clock signal. The clock adjusting unit adjusts the clock divisor according to the output pixel clock signal, the output vertical reference signal, and an input vertical reference signal having an input frame rate.
    Type: Application
    Filed: April 26, 2011
    Publication date: February 2, 2012
    Applicant: MSTAR SEMICONDUCTOR, INC.
    Inventors: Jian-Kao Chen, Chih Chiang Hsu
  • Publication number: 20120019167
    Abstract: A backlight control circuit and method thereof are provided to control the backlight of a backlight module so as to enhance the dynamic contrast ratio and save power. The backlight control circuit includes an average luminance detection circuit, a luminance distribution detection unit, a pulse width control circuit and a pulse width modulator. The average luminance detection circuit detects the average luminance of a frame which includes a plurality of pixels; the luminance distribution detection unit detects the pixel luminance distribution of the frame; the pulse width control circuit generates a pulse width control signal according to the average luminance and the pixel luminance distribution of the frame; and the pulse width modulator generates a pulse width modulation (PWM) signal according to the pulse width control signal, so as to control the backlight of the backlight module.
    Type: Application
    Filed: March 28, 2011
    Publication date: January 26, 2012
    Applicant: MSTAR SEMICONDUCTOR, INC.
    Inventors: Jian-Kao Chen, Chih Chiang Hsu
  • Patent number: 8100442
    Abstract: A rotary lock mechanism disclosed includes a housing, a linear latch, and a rotary latch. The linear latch is disposed next to the housing and slides corresponding to the housing. The rotary latch is pivoted at a side of the housing, which faces the position structure. The rotary latch includes a dual-angle ramp disposed facing the linear latch. The linear latch may touch the dual-angle ramp to rotate the rotary latch when the linear latch slides corresponding to the housing.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: January 24, 2012
    Assignee: Quanta Computer Inc.
    Inventors: Chih-Chiang Hsu, Tsung-Ju Chiang
  • Patent number: 7845690
    Abstract: A folding electronic device includes a cover and a main body. The cover includes a groove. The main body includes an engaging structure. The engaging structure includes a pushing element, an elastic element connected to the pushing element, an engaging element and a base. The engaging element includes a first connector and an engaging portion. The first connector is disposed on two sides of the engaging portions. The engaging portion is connected to or is detached from the groove. The base comprises an accommodating portion and a second connector. The pushing element and the elastic element are disposed in the accommodating portion. The second connector is disposed on two sides of the base. The engaging element is installed across the base. The first connector pivots on the second connector.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: December 7, 2010
    Assignee: Quanta Computer Inc.
    Inventors: Chih-Chiang Hsu, Wen-Chi Huang
  • Patent number: 7797593
    Abstract: A timing measurement circuit inside a memory chip delays balanced test signals for generating delayed test signals. Each of the delayed test signals is input a corresponding input pin of a memory subsystem of the memory chip. By adjusting delay amount of the delayed test signals, AC timing parameters of the memory subsystem are tested and measured. When the timing measurement circuit is in ring oscillation, a resolution thereof is measured.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: September 14, 2010
    Assignee: Faraday Technology Corp.
    Inventors: Chih-Chiang Hsu, Shang-Chih Hsieh
  • Patent number: 7779312
    Abstract: A built-in redundancy analyzer and a redundancy analysis method thereof for a chip having a plurality of repairable memories are provided. The method includes the following steps. First, the identification code of a repairable memory containing a fault (“fault memory” for short) is identified and a parameter is provided according to the identification code. The parameter includes the length of row address, the length of column address, the length of word, the number of redundancy rows, and the number of redundancy columns of the fault memory. Since the parameter of every individual repairable memory is different, the fault location is converted into a general format according to the parameter for easier processing. A redundancy analysis is then performed according to the parameter and the converted fault location, and the analysis result is converted from the general format to the format of the fault memory and output to the fault memory.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: August 17, 2010
    Assignee: Faraday Technology Corp.
    Inventors: Tsu-Wei Tseng, Chih-Chiang Hsu, Jin-Fu Li, Chien-Yuan Pao
  • Patent number: 7755883
    Abstract: The invention provides a connection structure installed in a data processing apparatus. The data processing apparatus includes a keyboard and a base. The keyboard includes a bottom. The base includes a top plate. The connection structure connects the bottom and the top plate. The connection structure includes a mounted boss and a mounting hole. The mounted boss is disposed on the bottom of the keyboard. The mounted boss includes a groove. The mounting hole is disposed on the top plate of the base. The mounting hole includes a protrusion. When the bottom of the keyboard is assembled to the top of the base, the mounted boss would fit into the mounting hole, such that the protrusion is locked with the groove.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: July 13, 2010
    Assignee: Quanta Computer Inc.
    Inventors: Chih Chiang Hsu, Chia Cheng Tang, Chien Jung Su
  • Publication number: 20100141472
    Abstract: A decoding method and apparatus capable of automatically adjusting a sampling period is provided. The decoding apparatus decodes a serial code including at least one header pulse and a plurality of data pulses. The decoding apparatus includes a detecting unit for detecting the header pulse to generate an initialization signal, a determining unit for determining a sampling period according to the initialization signal and a pulse width of one of the data pulses, and a decoding unit for decoding the data pulses according to the sampling period.
    Type: Application
    Filed: August 14, 2009
    Publication date: June 10, 2010
    Applicant: MSTAR SEMICONDUCTOR, INC.
    Inventors: Chih Chiang Hsu, Yu-Ming Lin
  • Publication number: 20090235698
    Abstract: A rotary lock mechanism disclosed includes a housing, a linear latch, and a rotary latch. The linear latch is disposed next to the housing and slides corresponding to the housing. The rotary latch is pivoted at a side of the housing, which faces the position structure. The rotary latch includes a dual-angle ramp disposed facing the linear latch. The linear latch may touch the dual-angle ramp to rotate the rotary latch when the linear latch slides corresponding to the housing.
    Type: Application
    Filed: June 30, 2008
    Publication date: September 24, 2009
    Applicant: Quanta Computer Inc.
    Inventors: Chih-Chiang Hsu, Tsung-Ju Chiang
  • Publication number: 20090158104
    Abstract: A timing measurement circuit inside a memory chip delays balanced test signals for generating delayed test signals. Each of the delayed test signals is input a corresponding input pin of a memory subsystem of the memory chip. By adjusting delay amount of the delayed test signals, AC timing parameters of the memory subsystem are tested and measured. When the timing measurement circuit is in ring oscillation, a resolution thereof is measured.
    Type: Application
    Filed: December 18, 2007
    Publication date: June 18, 2009
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventors: Chih-Chiang Hsu, Shang-Chih Hsieh
  • Publication number: 20090058101
    Abstract: A folding electronic device includes a cover and a main body. The cover includes a groove. The main body includes an engaging structure. The engaging structure includes a pushing element, an elastic element connected to the pushing element, an engaging element and a base. The engaging element includes a first connector and an engaging portion. The first connector is disposed on two sides of the engaging portions. The engaging portion is connected to or is detached from the groove. The base comprises an accommodating portion and a second connector. The pushing element and the elastic element are disposed in the accommodating portion. The second connector is disposed on two sides of the base. The engaging element is installed across the base. The first connector pivots on the second connector.
    Type: Application
    Filed: January 7, 2008
    Publication date: March 5, 2009
    Applicant: QUANTA COMPUTER INC.
    Inventors: Chih-Chiang Hsu, Wen-Chi Huang
  • Publication number: 20090059482
    Abstract: An electronic device comprises a battery and a main body. The battery comprises an engaging element. The engaging element comprises a hook, a depressed surface and an inclined surface. The hook protrudes from the battery. The inclined surface and the depressed surface are connected to two sides of the hook. The main body comprises a linkage. The linkage is slidably disposed on the main body. The linkage comprises a hole with two side walls. The hook is engaged with the hole.
    Type: Application
    Filed: January 7, 2008
    Publication date: March 5, 2009
    Applicant: QUANTA COMPUTER INC.
    Inventors: Chih-Chiang Hsu, Tsung-Ju Chiang