Abstract: A clock de-skewing delay locked loop circuit is revealed. In the clock de-skewing delay locked loop circuit, a timing control circuit generates a first and a second clock signals according to an external and an internal clock signal. A clock delay line delays the first clock signal or the external clock signal to generate delay signals. A delay mirror circuit synchronizes the internal clock signal with the external clock signal. A phase adjustment circuit inverts the internal clock signal according to the phase difference. An inverting buffer circuit buffers the external clock signal or the first clock signal for adding an initial delay time so as to make a duty cycle of internal clock signal and of the external clock signal complement each other. Thus the duty cycle of the external clock signal in the proposed circuit is not necessarily 50%.

Abstract: A clock de-skewing delay locked loop circuit is revealed. In the clock de-skewing delay locked loop circuit, a timing control circuit generates a first and a second clock signals according to an external and an internal clock signal. A clock delay line delays the first clock signal or the external clock signal to generate delay signals. A delay mirror circuit synchronizes the internal clock signal with the external clock signal. A phase adjustment circuit inverts the internal clock signal according to the phase difference. An inverting buffer circuit buffers the external clock signal or the first clock signal for adding an initial delay time so as to make a duty cycle of internal clock signal and of the external clock signal complement each other. Thus the duty cycle of the external clock signal in the proposed circuit is not necessarily 50%.

Abstract: A computer-implemented method for testing an operating condition of light emitting diodes (LEDs) on a motherboard includes assigning an LED identification for each LED according to positions of the LEDs on the motherboard, selecting a first LED identification for a first LED and a second LED identification for a second LED, setting the first LED in a bright state, the second LED in a dim state, and any remaining LEDs in a flicker state, and controlling the LEDs to operate. The method further includes determining whether the total count of the LEDs in the bright state is equal to one, and whether the total count of the LEDs in the dim state is equal to one, comparing the first LED identification input with the first LED identification, and comparing the second LED identification input with the LED identification, and reporting a comparison result.

Abstract: A sock includes a cushion pad connected to an outside of the sock and the cushion pad includes chambers which have pressurized air filled therein. The cushion pad is made by flexible material and the chambers are in communication with each other or partially in communication with each other.

Abstract: A computer-implemented method for testing an operating condition of light emitting diodes (LEDs) on a motherboard includes assigning an LED identification for each LED according to positions of the LEDs on the motherboard, selecting a first LED identification for a first LED and a second LED identification for a second LED, setting the first LED in a bright state, the second LED in a dim state, and any remaining LEDs in a flicker state, and controlling the LEDs to operate. The method further includes determining whether the total count of the LEDs in the bright state is equal to one, and whether the total count of the LEDs in the dim state is equal to one, comparing the first LED identification input with the first LED identification, and comparing the second LED identification input with the LED identification, and reporting a comparison result.

Abstract: A system for testing a NAS includes: a data storage device (3) connected with a NAS (6) for storing function test program and test data; a host computer (1) connected with the NAS being used to issue commands for the NAS to self-test itself via the function test program and test data; and at least one USB flash memory (4) connected with the NAS for testing the PCI ports of the NAS. A method for testing a NAS is also disclosed.

Abstract: A system for loading various operating systems includes a remote console (1) and multiple clients (3). The remote console includes a client controlling module (10) for checking connection statuses between the remote console and the clients, and for determining whether the already connected clients can receive orders from the remote console, and for selecting object clients from the clients that can receive orders; a code setting module (11) for selecting operating systems to be loaded in the object clients, and setting codes of disk partition sections in the object clients respectively; and an order sending module (12) for sending orders and the codes. Each client includes a receiving module (30) for receiving the orders and the codes, and executing the orders; and an amending module (32) for amending disk partition tables to configure the disk partition sections as boot sections according to the codes. A related method is also disclosed.

Abstract: A manufacturing method of forming an encapsulation layer on a back surface of a wafer, the method comprising the steps of: providing the wafer having the back surface and an active surface opposing to the back surface; providing an encapsulation disposed only on the back surface of the wafer, and not disposing the encapsulation over the active surface of the wafer; providing a mold having a mold surface disposed over the encapsulation; heating the mold and moving the mold surface to press the encapsulation simultaneously so as to have the encapsulation distributed over the back surface of the wafer to form the encapsulation layer on the back surface of the wafer; and singulating the wafer into a plurality of chips, wherein the encapsulation layer is formed on a back surface of each chip, and is not formed on a side surface of each chip.

Abstract: A method for manufacturing a semiconductor chip with bumps comprises providing a semiconductor chip, which defines an active surface and a back surface and has a plurality of pads disposed on the active surface, and a plurality of preformed solder balls. A passivation is disposed on the active surface of the semiconductor chip with the pads exposed. A plurality of UBMs (Under Bump Metallurgy) are disposed on the pads and define a plurality of bump pads. The diameter of the bump pads is about 100% to about 130% of the diameter of the preformed solder balls. The preformed solder balls are placed on the bump pads and then reflowed to form a plurality of bumps on the semiconductor chip.

Abstract: A method of correcting a mask layout is provided. The mask layout includes a plurality of element patterns. An inspection program is executed to classify the element patterns of the mask layout into a plurality of element pattern types according to a pattern density of the element patterns. Following this, each of the element pattern types is corrected so as to prevent a plasma micro-loading effect.

Abstract: A manufacturing method of forming an encapsulation layer on a back surface of a wafer mainly comprises the following steps. Firstly, there is provided a wafer having an active surface and a back surface, wherein the active surface has a plurality of bumps formed thereon. Next, an encapsulation is provided on the back surface of the wafer and a mold is provided to have a mold surface of the mold disposed over the back surface. Afterwards, the mold surface is heated and moved to press the encapsulation simultaneously so as to have the encapsulation entirely distributed over the back surface of the wafer to form the encapsulation layer, with a flat surface, covering the back surface of the wafer.

Abstract: A method for manufacturing a semiconductor chip with bumps comprises providing a semiconductor chip, which defines an active surface and a back surface and has a plurality of pads disposed on the active surface, and a plurality of preformed solder balls. A passivation is disposed on the active surface of the semiconductor chip with the pads exposed. A plurality of UBMs (Under Bump Metallurgy) are disposed on the pads and define a plurality of bump pads. The diameter of the bump pads is about 100% to about 130% of the diameter of the preformed solder balls. The preformed solder balls are placed on the bump pads and then reflowed to form a plurality of bumps on the semiconductor chip.

Abstract: A method of correcting a mask layout is provided. The mask layout includes a plurality of element patterns. An inspection program is executed to classify the element patterns of the mask layout into a plurality of element pattern types according to a pattern density of the element patterns. Following this, each of the element pattern types is corrected so as to prevent a plasma micro-loading effect.

Abstract: A method of spin-on-glass planarization. A spin-on-glass layer is formed on a substrate. An accuflo layer with a better fluidity than the spin-on-glass material is formed on the spin-on-glass layer. The accuflo layer and the spin-on-glass layer are etched back by two etching steps with different etching rate. The accuflo layer after being etched is stripped. A dielectric layer is formed.

Abstract: A structure color sensor of a diode includes following: Firstly, a color sensor layer including a number of color sensor areas is formed on a substrate for absorbing and sensing the different color light. Then, a black matrix film covered by a transparent planarization film is on the color sensor layer by using dispersed pigment method and is placed on the interfaces between color sensor areas to reduce the interference effects between monochromatic lights. Then, a color filter including at least a red filter, a green filter, and a blue filter is on this transparent planarization film. And then, a cover film is formed on the color filter for protection.

Abstract: A mixed mode photo-mask for a stepper. Both alignment marks of 15 mm.times.15 mm and alignment marks of 20 mm.times.20 mm are tooled on the photo mask. The photo mask further comprises a reticle glass plate, a chrome border with a pattern to be transferred, and a pellicle.

Abstract: A process and a monitor structure to measure semiconductor device dimensions, especially contact and via hole dimensions, and proximity effects. The monitor has structures and layers which match the thickness and configuration of the product devices and allow measurement of step heights and proximity measurements. The monitor pattern includes an alignment region for use with automeasurement equipment. Measurements of openings are performed on the monitor at various points during the fabrication process.