Abstract: The invention provides an electronic apparatus. The electronic apparatus includes a Dynamic Random Access Memory (DRAM) and a DRAM controller. The DRAM receives at least one control and address signal and a clock signal, delays the clock signal by a predetermined value to obtain a delayed clock signal, samples the control and address signal according to the clock signal to obtain a first sample signal, samples the control and address signal according to the delayed clock signal to obtain a second sample signal, and compares the first sample signal with the second sample signal to obtain a status signal. The DRAM controller sends the control and address signal and the clock signal to the DRAM, receives the status signal from the DRAM, and adjusts a phase difference between the clock signal and the control and address signal according to the status signal.

Abstract: An electronic device comprises an interface unit, a control circuit and a microprocessor. The interface unit receives a first operational firmware from a host. The control circuit transfers the first operational firmware to a memory. The microprocessor executes the first operational firmware which stored in the memory. The microprocessor controls operations of the electronic device according to the first operational firmware. And the control circuit is electrically coupled to a non-volatile memory which stores a second operational firmware for performing a specific function also performed by the first operational firmware.

Abstract: An optical storage device that includes a memory and a controller. The memory includes a command queue to store advanced technology attachment (ATA) commands sent by a host device. The controller executes the commands, in which at least a subset of the commands are executed in a sequence that is different from a sequence in which the commands are sent by the host device.

Abstract: An optical storage device that includes a memory and a controller. The memory includes a command queue to store advanced technology attachment (ATA) commands sent by a host device. The controller executes the commands, in which at least a subset of the commands are executed in a sequence that is different from a sequence in which the commands are sent by the host device.

Abstract: A SPI device. The SPI device comprises a serial clock pin, a chip select pin, a data input pin, and a data output pin. The serial clock pin transmits a serial clock from a master device to a slave device. The chip select pin determines whether the slave device is selected by the master device. The data input pin transfers instructions, addresses, data to be programmed, dummy input or a combination thereof from the master device to the slave device. The data output pin transfers data from the slave device to the master device. The SPI device acts as the master device or the slave device. One pin other than the data output, serial clock and chip select pins acts as an additional data output pin when the data output pin transfers data from the slave device to the master device.

Abstract: An optical storage device that includes a memory and a controller. The memory includes a command queue to store advanced technology attachment (ATA) commands sent by a host device. The controller executes the commands, in which at least a subset of the commands are executed in a sequence that is different from a sequence in which the commands are sent by the host device.

Abstract: An optical disc drive includes a microprocessor, a control IC, an RF IC, and an interface unit. The microprocessor is electrically coupled to the control IC. The control IC is electrically coupled to the RF IC, a volatile RAM, an optional non-volatile ROM, and to a bus interface for communications with an external host. The interface unit is electrically coupled to the bus interface. Initialization of the optical disc drive is performed using initialization data stored in a non-volatile manner in the ROM, if present, or downloaded from the host if the ROM is not present. After the initialization, the interface unit signals an application program in the host to download the optical drive's operational firmware and writes received data into the RAM. The microprocessor is initialized with the operational firmware's starting address and the microprocessor executes the downloaded operational firmware.

Abstract: An optical disc drive includes a microprocessor, a control IC, an RF IC, and an interface unit. The microprocessor is electrically coupled to the control IC. The control IC is electrically coupled to the RF IC, a volatile RAM, an optional non-volatile ROM, and to a bus interface for communications with an external host. The interface unit is electrically coupled to the bus interface. Initialization of the optical disc drive is performed using initialization data stored in a non-volatile manner in the ROM, if present, or downloaded from the host if the ROM is not present. After the initialization, the interface unit signals an application program in the host to download the optical drive's operational firmware and writes received data into the RAM. The microprocessor is initialized with the operational firmware's starting address and the microprocessor executes the downloaded operational firmware. The ROM may also store read operation firmware to enable the optical disc drive to read data stored in the disc.

Abstract: A method of accessing encrypted instructions includes utilizing an instruction access controller to access an encrypted instruction, utilizing a microprocessor to drive the instruction access controller to access the encrypted instruction, decrypting the encrypted instruction to generate a decrypted instruction, and utilizing the microprocessor to operate according to the decrypted instruction.

Abstract: A receiver for a memory controller. The memory controller sends a data request signal to a memory which responds to the data request signal by sending data and a data strobe signal back to the memory controller. The receiver comprises a delay circuit receiving and delaying the data strobe signal, an emulated data strobe signal generator receiving the data request signal to generate an emulated data strobe signal, a push pointer generator generating a plurality of push pointers having priorities, receiving and responding to the emulated data strobe signal by outputting the push pointers in an order according to the priorities, and a buffer receiving and responding to the delayed data strobe signal and the push pointers by storing the data in memory addresses corresponding to the push pointers.

Abstract: A receiver for a memory controller. The memory controller sends a data request signal to a memory which responds to the data request signal by sending data and a data strobe signal back to the memory controller. The receiver comprises a delay circuit receiving and delaying the data strobe signal, an emulated data strobe signal generator receiving the data request signal to generate an emulated data strobe signal, a push pointer generator generating a plurality of push pointers having priorities, receiving and responding to the emulated data strobe signal by outputting the push pointers in an order according to the priorities, and a buffer receiving and responding to the delayed data strobe signal and the push pointers by storing the data in memory addresses corresponding to the push pointers.

Abstract: A method and apparatus for refreshing dynamic memory is provided. The apparatus includes an ahead refresh controller having an ahead queue for refreshing dynamic random access memory (DRAM) when the memory request bus is idle. In such a way that no dynamic RAM bandwidth is wasted. The apparatus also comprises a normal refresh controller having a normal queue. Giving the normal refresh request in the normal priority unless the normal queue is full. The present invention allows the refresh cycles to gather on the basis of events to minimize the overheads. In other words, even when the system is running in peak performance, the normal refresh controller can largely compact the refresh cycles by means of the normal queue to decrease occurrence of interruption.