Abstract: An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal and an array of write assist circuits electrically coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. The operating voltage corresponds to an output signal. Each write assist circuit includes a set of P-type transistors coupled together in parallel and further coupled to a supply voltage, and configured to set the output signal in response to an input control signal, and a first N-type transistor coupled to the set of P-type transistors. A first terminal of the first N-type transistor is configured to receive the input control signal. A second terminal of the first N-type transistor is coupled to the supply voltage.

Abstract: An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal, and an array of write assist circuits coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell, and generate the output signal in response to a first control signal. The operating voltage corresponds to an output signal. Each write assist circuit includes an AND gate coupled to a programmable voltage tuner. The programmable voltage tuner includes a set of P-type transistors coupled to a first P-type transistor. The set of P-type transistors is coupled together in parallel, and receives a set of select control signals. A first terminal of the first P-type transistor is configured to receive an AND signal from the AND gate.

Abstract: A method for forming sense amplifiers of a memory device includes: determining a type of each bitline selector used to provide a data signal to a corresponding sense amplifier; forming a plurality of separate active areas in a substrate of the memory device along one of a column direction and a row direction according to the type of the bitline selector, the substrate including a plurality of cell columns, each of the cell columns having a plurality of memory cells arranged along the column direction, each of the active areas being formed across a boundary between two adjacent cell columns and located within the adjacent cell columns; and arranging a plurality of gate structures on the active areas to form transistors of the sense amplifiers, each gate structure extending in the row direction.

Abstract: The present disclosure provides a memory array. The memory array includes a first memory cell, a first word line, a second word line, a first bit line, a first complementary bit line, a second bit line, a second complementary bit line, a first sense amplifier, a second sense amplifier and a first logic circuit. When the memory array operates in a binary content-addressable memory (BCAM) mode, during a search operation, a first logic output indicates whether a logic level of the first word line matches a first logic value at a first terminal of a first data storage of the first memory cell, and whether a logic level of the second word line matches a first complementary logic value at a second terminal of the first data storage of the first memory cell.

Abstract: A memory device includes a pair of memory cells, an analog-to-digital converter (ADC), and a processing circuit. The pair of memory cells has a first memory cell and a second memory cell. The ADC, having a first input terminal and a second input terminal, is configured to convert a first data signal at the first input terminal and a second data signal at the second input terminal into a digital output indicating a data value associated with a particular state stored in the pair of memory cells. The processing circuit, coupled to a storage node of the first memory cell, a storage node of the second memory cell, and the first and the second input terminals, is configured to selectively adjust the first data signal and the second data signal according to first data stored in the first memory cell and second data stored in the second memory cell.

Abstract: The present application discloses an interface transformer. The interface transformer includes a first clock generator, a combinational circuit, and a second clock generator. The first clock generator generates an intermediate clock signal according to an input clock signal. A rising edge of the input clock signal precedes a rising edge of the intermediate clock signal, and a falling edge of the intermediate clock signal precedes a falling edge of the input clock signal. The combinational circuit generates a mask clock signal by delaying the intermediate clock signal. The second clock generator generates a transformed clock signal according to the input clock signal and the mask clock signal. The transformed clock signal has two pulses within a cycle of the input clock signal.

Abstract: A sense enable circuit for enabling a sense amplifier is provided. The sense enable circuit includes a signal generator circuit, a group of reference memory cells and a control circuit. The signal generator circuit is configured to generate a sense amplifier enable signal according to a trigger signal. The sense amplifier is enabled by the sense amplifier enable signal to sense data stored in a memory cell. Each reference memory cell is coupled to a reference wordline and a reference bitline. The reference wordline is activated in response to activation of a wordline coupled to the memory cell. The reference memory cell is configured to, in response to activation of the reference wordline, couple a first reference signal to the reference bitline. The control circuit is configured to adjust a signal level of the reference bitline, and generate the trigger signal according to the signal level of the reference bitline.

Abstract: An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal, and an array of write assist circuits coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell, and generate the output signal in response to a first control signal. The operating voltage corresponds to an output signal. Each write assist circuit includes an AND gate coupled to a programmable voltage tuner. The programmable voltage tuner includes a set of P-type transistors coupled to a first P-type transistor. The set of P-type transistors is coupled together in parallel, and receives a set of select control signals. A first terminal of the first P-type transistor is configured to receive an AND signal from the AND gate.

Abstract: An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.

Abstract: An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.

Abstract: An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.

Abstract: An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.

Abstract: An integrated circuit that includes an array of memory cells and an array of write logic cells. The integrated circuit also includes a write address decoder comprising a plurality of write outputs. The array of write logic cells is electrically connected to the plurality of write outputs. The array of write logic cells is electrically connected to the array of memory cells. The array of write logic cells is configured to set an operating voltage of the memory cells.

Abstract: A memory includes a plurality of memory blocks, a plurality of sensing circuits, a plurality of global bit lines, a common pre-charging circuit and a selection circuit. Each global bit line of the plurality of global bit lines is coupled to at least one of the memory blocks by a corresponding sensing circuit of the plurality of sensing circuits. The common pre-charging circuit is configured to individually pre-charge each global bit line of the plurality of global bit lines to a pre-charge voltage. The selection circuit is configured to selectively couple the common pre-charging circuit to a selected global bit line of the plurality of global bit lines.

Abstract: A voltage providing circuit includes a first circuit configured to receive a first input signal and a second input signal and to generate an output signal. The first circuit includes a first transistor configured to switchably couple the second input signal to a first node responsive to the first input signal, a second transistor having a gate terminal coupled with the first node, and a third transistor having a source terminal coupled with a source terminal of the second transistor. The third transistor is configured to set a reference voltage value at the source terminal of the second transistor if the first input signal indicates that the second input signal is pulled from a first voltage value toward a second voltage value and if the second input signal reaches a predetermined voltage value. A second circuit is configured to receive the output signal and to generate an output voltage.

Abstract: A circuit includes a tracking bit line, a first capacitive circuit, a tracking circuit and a detection circuit. The first capacitive circuit is coupled to the tracking bit line. The first capacitive circuit has a capacitive load on the tracking bit line. The tracking circuit is coupled to the tracking bit line. The tracking circuit being configured to charge or discharge a voltage on the tracking bit line based on a first control signal or the capacitive load. The detection circuit is coupled to the tracking bit line, and is configured to generate a SAE signal responsive to the voltage of the tracking bit line and an inverted first control signal.

Abstract: A signal generating circuit includes a first circuit, a tracking circuit, and a delay circuit. The delay circuit is coupled with the first circuit and the tracking circuit. The first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit, and to generate a second clock signal and at least one first tracking signal. The tracking circuit is configured to receive the at least one first tracking signal and to generate a second tracking signal. The delay circuit is configured to receive the second clock signal and the second tracking signal and to generate the output signal.

Abstract: A circuit includes a tracking bit line, a first capacitive circuit, a tracking circuit and a detection circuit. The first capacitive circuit is coupled to the tracking bit line. The first capacitive circuit has a capacitive load on the tracking bit line. The tracking circuit is coupled to the tracking bit line. The tracking circuit being configured to charge or discharge a voltage on the tracking bit line based on a first control signal or the capacitive load. The detection circuit is coupled to the tracking bit line, and is configured to generate a SAE signal responsive to the voltage of the tracking bit line and an inverted first control signal.

Abstract: A circuit includes a tracking bit line, a tracking unit connected to the tracking bit line and a detection unit. The tracking unit is configured to receive a first control signal and configured to selectively charge or discharge a voltage on the tracking bit line in response to the first control signal. The detection unit is coupled to the tracking bit line and configured to generate a sense amplifier enable (SAE) signal in response to the voltage level on the tracking bit line.

Abstract: A circuit includes a supply voltage circuit, a voltage adjustment circuit, and a timing adjustment circuit. The supply voltage circuit is coupled to a memory device configured to provide a voltage level to the memory device during a write data operation. The voltage adjustment circuit is coupled to the supply voltage circuit, and is configured to provide at least one voltage level control signal to control one of a plurality of different voltages. At least one of the plurality of different voltages has a voltage level lower than a specified nominal supply voltage level. The timing adjustment circuit is coupled to the supply voltage circuit, and is configured to provide at least one voltage transition timing control signal to the supply voltage circuit. The supply voltage circuit is configured to provide at least one of the plurality of different voltages to the memory device during the write data operation.