Patents by Inventor Chih-Chieh Chou

Chih-Chieh Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11956869
    Abstract: A display driver circuit for controlling a display panel having a plurality of light-emission diode (LED) strings includes a plurality of current regulators and a control circuit. Each of the plurality of current regulators is configured to control one of the plurality of LED strings. The control circuit, coupled to the plurality of current regulators, is configured to generate a plurality of pulses in a plurality of pulse width modulation (PWM) signals and output each of the plurality of PWM signals to a respective current regulator among the plurality of current regulators. Wherein, the plurality of pulses are scrambled.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: April 9, 2024
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chih-Hsien Chou, Jhih-Siou Cheng, Jin-Yi Lin, Ren-Chieh Yang
  • Publication number: 20240113143
    Abstract: Various embodiments of the present disclosure are directed towards an imaging device including a first image sensor element and a second image sensor element respectively comprising a pixel unit disposed within a semiconductor substrate. The first image sensor element is adjacent to the second image sensor element. A first micro-lens overlies the first image sensor element and is laterally shifted from a center of the pixel unit of the first image sensor element by a first lens shift amount. A second micro-lens overlies the second image sensor element and is laterally shifted from a center of the pixel unit of the second image sensor element by a second lens shift amount different from the first lens shift amount.
    Type: Application
    Filed: January 6, 2023
    Publication date: April 4, 2024
    Inventors: Cheng Yu Huang, Wen-Hau Wu, Chun-Hao Chuang, Keng-Yu Chou, Wei-Chieh Chiang, Chih-Kung Chang
  • Patent number: 11948936
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a fin disposed in a first region of the semiconductor device, channel members disposed in a second region of the semiconductor device and stacked in a vertical direction, first and second metal gates disposed on a top surface of the fin, a third metal gate wrapping around each of the channel members, a first implant region in the fin with a first conductivity type, and a second implant region in the fin with a second conductivity opposite the first conductivity type. The fin includes first and second type epitaxial layers alternatingly disposed in the vertical direction. The first and second type epitaxial layers have different material compositions. The first type epitaxial layers and the channel members have the same material composition.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hung Wang, Chih Chieh Yeh, Zi-Ang Su, Chia-Ju Chou, Ming-Shuan Li
  • Patent number: 11941298
    Abstract: A host system initiates an abort of a command that has been placed into a submission queue (SQ) of the host system. The host system identifies at least one of a first outcome and a second outcome. When the first outcome indicates that the command is not completed and the second outcome indicates that the SQ entry has been fetched from the SQ, the host system sends an abort request to a storage device, and issues a cleanup request to direct the host controller to reclaim host hardware resources allocated to the command. The host system adds a completion queue (CQ) entry to a CQ and sets an overall command status (OCS) value of the CQ entry based on at least one of the first outcome and the second outcome.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: March 26, 2024
    Assignee: MediaTek Inc.
    Inventors: Chih-Chieh Chou, Chia-Chun Wang, Liang-Yen Wang, Chin Chin Cheng, Szu-Chi Liu
  • Publication number: 20240088182
    Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
  • Patent number: 11923386
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first photodetector disposed in a first pixel region of a semiconductor substrate and a second photodetector disposed in a second pixel region of the semiconductor substrate. The second photodetector is laterally separated from the first photodetector. A first diffuser is disposed along a back-side of the semiconductor substrate and over the first photodetector. A second diffuser is disposed along the back-side of the semiconductor substrate and over the second photodetector. A first midline of the first pixel region and a second midline of the second pixel region are both disposed laterally between the first diffuser and the second diffuser.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Kazuaki Hashimoto, Wei-Chieh Chiang, Cheng Yu Huang, Wen-Hau Wu, Chih-Kung Chang
  • Patent number: 11915977
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih Pei Chou, Chia-Chieh Lin
  • Publication number: 20240045618
    Abstract: A host system is coupled to a storage device and manages completion queues (CQs) for the storage device. The host system includes a host controller and memory that stores submission queues (SQs) and the CQs. The host controller fetches a command from a given SQ that corresponds to a target CQ. The host controller saves the command in an SQ internal buffer of the host controller, calculates an available capacity (AC) associated with the given SQ for the host system to store a response to the command from the storage device, and sends the command to the storage device when the available capacity is non-zero. The available capacity is calculated based on, at least in part, available slots in the target CQ.
    Type: Application
    Filed: May 24, 2023
    Publication date: February 8, 2024
    Inventors: Chin Chin Cheng, Chih-Chieh Chou, Tzu-Shiun Liu
  • Publication number: 20220365724
    Abstract: A host system initiates an abort of a command that has been placed into a submission queue (SQ) of the host system. The host system identifies at least one of a first outcome and a second outcome. When the first outcome indicates that the command is not completed and the second outcome indicates that the SQ entry has been fetched from the SQ, the host system sends an abort request to a storage device, and issues a cleanup request to direct the host controller to reclaim host hardware resources allocated to the command. The host system adds a completion queue (CQ) entry to a CQ and sets an overall command status (OCS) value of the CQ entry based on at least one of the first outcome and the second outcome.
    Type: Application
    Filed: April 19, 2022
    Publication date: November 17, 2022
    Inventors: Chih-Chieh Chou, Chia-Chun Wang, Liang-Yen Wang, Chin Chin Cheng, Szu-Chi Liu
  • Publication number: 20220350536
    Abstract: A host system coupled to a storage system provides hardware support for command abort. The host system includes a host controller, which detects that a host driver has disabled an enable indicator of a submission queue (SQ). In response to the detection, the host controller stops further fetching from the SQ. The host controller sends all entries that have been fetched from the SQ to the storage device, and sets a status indicator of the SQ to indicate stopped fetching of the SQ.
    Type: Application
    Filed: April 19, 2022
    Publication date: November 3, 2022
    Inventors: Chih-Chieh Chou, Chia-Chun Wang, Liang-Yen Wang, Szu-Chi Liu, Chin Chin Cheng
  • Patent number: 11474952
    Abstract: Methods, systems, and computer readable media for performing page fault handling are disclosed. According to one method, the method includes: after a translation lookaside buffer (TLB) miss associated with a virtual memory page occurs, identifying, in a page table, a page table entry (PTE) associated with the virtual memory page; determining, using a first indicator in the PTE, that the virtual memory page is not present in a main memory; determining, using a second indicator in the PTE, that the virtual memory page is associated with a valid memory address and that the virtual memory page is capable of using pre-allocated pages; obtaining, from a pre-allocation table, a page frame number associated with a pre-allocated page; and updating the PTE to indicate the page frame number.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: October 18, 2022
    Assignees: The Texas A&M University System, Hewlett Packard Enterprise Development LP
    Inventors: Narasimha Reddy Annapareddy, Chih-Chieh Chou, Chandrahas Tirumulasetty, Paul Gratz, Ayman Abouelwafa
  • Publication number: 20210374071
    Abstract: Methods, systems, and computer readable media for performing page fault handling are disclosed. According to one method, the method includes: after a translation lookaside buffer (TLB) miss associated with a virtual memory page occurs, identifying, in a page table, a page table entry (PTE) associated with the virtual memory page; determining, using a first indicator in the PTE, that the virtual memory page is not present in a main memory; determining, using a second indicator in the PTE, that the virtual memory page is associated with a valid memory address and that the virtual memory page is capable of using pre-allocated pages; obtaining, from a pre-allocation table, a page frame number associated with a pre-allocated page; and updating the PTE to indicate the page frame number.
    Type: Application
    Filed: June 1, 2021
    Publication date: December 2, 2021
    Inventors: Narasimha Reddy Annapareddy, Chih-Chieh Chou, Chandrahas Tirumulasetty, Paul Gratz, Ayman Abouelwafa
  • Publication number: 20180103127
    Abstract: A method of managing Universal Serial Bus (USB) data transmission and wireless communication of an electronic device is disclosed.
    Type: Application
    Filed: December 11, 2017
    Publication date: April 12, 2018
    Inventors: Cheok Yan Goh, Yu-Hsun Chen, Chih-Chieh Chou, Horng-Bin Wang, Ching-Hwa Yu
  • Publication number: 20170207060
    Abstract: A test structure for electron beam inspection and a method for defect determination using electron beam inspection are provided. The test structure for electron beam inspection includes a semiconductor substrate, at least two conductive regions disposed on the semiconductor substrate, a connection structure disposed on the two conductive regions, and a cap dielectric layer disposed on the connection structure. The method for defect determination using the electron beam inspection includes the following steps. An electron beam inspection is preformed to a test structure with an instant detector and a lock-in amplifier. Signals received by the detector within a period of time are amplified by the lock-in amplifier. A defect in the test structure is determined by monitoring the signals received by the detector and amplified by the lock-in amplifier. The inspection accuracy is improved by the test structure and the method for defect determination in the present invention.
    Type: Application
    Filed: January 20, 2016
    Publication date: July 20, 2017
    Inventors: Kuan-Chun Lin, Chih-Chieh Chou, Shih-Cheng Chen, Chung-Chih Hung, Yung-Teng Tsai, Chi-Hung Chan
  • Patent number: 9711326
    Abstract: A test structure for electron beam inspection and a method for defect determination using electron beam inspection are provided. The test structure for electron beam inspection includes a semiconductor substrate, at least two conductive regions disposed on the semiconductor substrate, a connection structure disposed on the two conductive regions, and a cap dielectric layer disposed on the connection structure. The method for defect determination using the electron beam inspection includes the following steps. An electron beam inspection is preformed to a test structure with an instant detector and a lock-in amplifier. Signals received by the detector within a period of time are amplified by the lock-in amplifier. A defect in the test structure is determined by monitoring the signals received by the detector and amplified by the lock-in amplifier. The inspection accuracy is improved by the test structure and the method for defect determination in the present invention.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: July 18, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Chun Lin, Chih-Chieh Chou, Shih-Cheng Chen, Chung-Chih Hung, Yung-Teng Tsai, Chi-Hung Chan
  • Patent number: 9632971
    Abstract: A method of handling transmission for a host in a data transmission system includes establishing a connection with a device of the data transmission system via a first frequency; receiving a negotiating information from the device; and re-establishing the connection with the device via a second frequency when the negotiating information reveals that the second frequency is available for the host to communicate with the device; wherein the second frequency is different than the first frequency.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: April 25, 2017
    Assignee: MEDIATEK INC.
    Inventors: Cheok Yan Goh, Yu-Hsun Chen, Mao-Lin Wu, Chih-Chieh Chou, Ching-Hwa Yu
  • Publication number: 20140241406
    Abstract: A wireless communications system co-located with an interface apparatus includes a radio subsystem. The radio subsystem includes a transmission circuit arranged for performing a radio transmission, and a reception circuit arranged for performing a radio reception when the interface apparatus operates in a first operational state. The interface apparatus operates in one of a plurality of operational states including the first operational state and a second operational state, and a power consumption of the interface apparatus in the first operational state is lower than a power consumption of the interface apparatus in the second operational state.
    Type: Application
    Filed: February 27, 2014
    Publication date: August 28, 2014
    Applicant: Mediatek Inc.
    Inventors: Ching-Hwa Yu, Cheok Yan Goh, Yu-Hsun Chen, Horng-Bin Wang, Mao-Lin Wu, Chih-Chieh Chou, Tsung-Yueh Hsieh, I-Lin Hsieh
  • Publication number: 20140244852
    Abstract: A method of reducing mutual interference between Universal Serial Bus (USB) data transmission and wireless communication for an electronic device is disclosed. The method comprises establishing a plurality of physical layer links for the USB data transmission in a plurality of supported USB modes; dynamically selecting one of the supported USB modes according to the wireless communication; and performing the USB data transmission in the selected USB mode.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 28, 2014
    Applicant: Ralink Technology Corp.
    Inventors: Cheok Yan Goh, Yu-Hsun Chen, Chih-Chieh Chou, Horng-Bin Wang, Ching-Hwa Yu
  • Publication number: 20140244872
    Abstract: A method of handling transmission for a host in a data transmission system includes establishing a connection with a device of the data transmission system via a first frequency; receiving a negotiating information from the device; and re-establishing the connection with the device via a second frequency when the negotiating information reveals that the second frequency is available for the host to communicate with the device; wherein the second frequency is different than the first frequency.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 28, 2014
    Applicant: Ralink Technology Corp.
    Inventors: Cheok Yan Goh, Yu-Hsun Chen, Mao-Lin Wu, Chih-Chieh Chou, Ching-Hwa Yu
  • Patent number: 7896691
    Abstract: An electronic device and an airproof connector module thereof are provided. The electronic device is connected to a peripheral device by the connector module. The connector module includes a casing, an adapting board, a first connector, a second connector, a first elastic sealing element, and a second elastic sealing element. The adapting board is disposed in a containing space in the casing. The casing has a connection hole and an opening. The first connector is disposed at the connection hole, and the second connector is disposed at the opening. The first connector and the second connector are coupled to the adapting board. The first elastic sealing element fills space between the first connector and the connection hole. The second elastic sealing element fills space between the second connector and the opening.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: March 1, 2011
    Assignee: Pegatron Corporation
    Inventors: Kai-Chen Tien, Chih-Chieh Chou, Hung-Chang Huang