Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.

Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.

Abstract: Some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. A first dielectric layer is disposed laterally between the conductive structures. A spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. An etch stop layer overlies the plurality of conductive structures. The etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: An electric device includes a semiconductor assembly, a circuit board, first conductive pads and second conductive pads. The circuit board has a chip-mounted area with a rectangular shape. The first conductive pads are arranged in a center zone or all corner zones of the chip-mounted area, and the second conductive pads are arranged within the rest in the chip-mounted area. The first conductive pads are respectively soldered to one part of solder joints of the semiconductor assembly through first solder-ball portions, and the second conductive pads are respectively soldered to another part of the solder joints of the semiconductor assembly through second solder-ball portions. Each of the second conductive pads is sized smaller than one of the first conductive pads, and a maximum width of each of the second solder-ball portions is greater than a maximum width of each of the first solder-ball portions.

Abstract: An inspecting device including a carrier, multiple telescopic probes, a locking component and a conductive structure is provided. The carrier has a through hole and a ground pad corresponding to the through hole. The through hole penetrates from the first surface to the second surface of the carrier, and the ground pad is disposed on the second surface. The telescopic probes are disposed in parallel on the first surface of the carrier. The locking component passes through the through hole and is disposed between two adjacent telescopic probes of the multiple telescopic probes. The locking component includes a screw. A head of the screw has a first pitch and a second pitch, and a density of the first pitch is different from a density of the second pitch. The conductive structure is partially embedded in the locking component, and the conductive structure, the locking component and the ground pad are electrically connected.

Abstract: A thermal peak suppression device includes a heat dissipation fin set, a heat dissipator, a thermal phase change material, a filling gas, a fin-array frame and a capillary tube. The heat dissipator includes a thermal conductive block thermally coupled to the heat dissipation fin set, and a closed cavity formed inside the thermal conductive block to have a hot zone and a cold zone. The thermal phase change material is disposed within the hot zone. The filling gas is disposed within the cold zone. The fin-array frame is connected to the thermal conductive block within the cold zone. Two opposite ends of the capillary tube are respectively located within the cold zone and the hot zone. When the thermal phase change material is transformed into a liquid state, the thermal phase change material is sent to the hot zone through the capillary tube.

Abstract: A probe card device includes a wiring board provided with a plurality of contacts, a probe head having a probe holder and a plurality of conductive probes arranged on the probe holder, respectively, and a circuit protection assembly including an insulation plate, a plurality of through holes and a plurality of self-resetting fusing elements. The insulation plate is sandwiched between the wiring board and the probe head. The through holes are respectively formed on the insulation plate and arranged in an array form. The self-resetting fusing elements are respectively disposed within the through holes. Each of the self-resetting fusing elements is electrically connected to one of the contacts and one of the conductive probes for reversibly breaking down electric currents from the wiring board to the conductive probe.

Abstract: A conductive probe includes a columnar body. The columnar body is defined with a longitudinal direction. The columnar body is provided with a first contacting surface and a second contacting surface in the longitudinal direction. The first contacting surface is opposite to the second contacting surface, and the first contacting surface is cross shaped or X-shaped for contacting to a conductive pillar of a device under test (DUT).

Abstract: A pogo pin-free testing device for IC chip test includes a load board, a ceramic interposer disposed on the load board, and copper core balls. The ceramic interposer has first and second surfaces and connecting points, and the second surface of the ceramic interposer faces the load board. Each connecting point has through holes penetrating the first and second surfaces, and an inner sidewall surface thereof has a metallization layer. The metallization layer is extended to a portion of the first surface and a portion of the second surface. In each of the connecting points, an area of an extending portion of the metallization layer extended to the second surface is less than an area of an extending portion of the metallization layer extended to the first surface. The copper core balls are disposed between the load board and the through holes of each connecting point of the ceramic interposer.

Abstract: A testing apparatus including a base and a preheating unit arranged on the base is provided. The preheating unit includes a gas generator, a blocking mechanism and a heating device. The gas generator is configured to discharge air toward the base to form an air wall. The blocking mechanism is located above the air wall and forms a heat preservation space with the air wall. The heating device is arranged in the heat preservation space.

Abstract: A testing system includes a testing apparatus and a crack noise monitoring device. The testing apparatus includes a testing stage and an element pickup module for pressing a semiconductor element on the testing stage. The crack noise monitoring device includes a database unit, a sound conduction set, a voiceprint generation unit and a processing unit. The database unit has a first voiceprint pattern. The sound conduction set is connected to the voiceprint generation unit and the testing apparatus for transmitting a sound wave from the semiconductor element to the voiceprint generation unit. The voiceprint generation unit receives and converts the sound wave into a second voiceprint pattern. The processing unit is electrically connected to the voiceprint generating unit and the database unit for determining whether the first voiceprint pattern is identical to the second voiceprint pattern.

Abstract: A pogo pin-free testing device for IC chip test includes a load board, a ceramic interposer disposed on the load board, and copper core balls. The ceramic interposer has first and second surfaces and connecting points, and the second surface of the ceramic interposer faces the load board. Each connecting point has through holes penetrating the first and second surfaces, and an inner sidewall surface thereof has a metallization layer. The metallization layer is extended to a portion of the first surface and a portion of the second surface. In each of the connecting points, an area of an extending portion of the metallization layer extended to the second surface is less than an area of an extending portion of the metallization layer extended to the first surface. The copper core balls are disposed between the load board and the through holes of each connecting point of the ceramic interposer.

Abstract: A testing socket includes a metal block, an assembly block, an analog ground probe pin and a digital ground probe pin. The metal block is formed with a concave portion and used to connect to an independent main ground. The assembly block is electrically isolated from the metal block, and detachably embedded in the recess, so that the metal block and the assembly block are assembled together to be a probe holder. The digital grounding probe is inserted in the metal block, electrically connected to the independent main ground through the metal block. The digital ground probe pin can be electrically connected to a device to be tested (DUT) and the independent main ground. The analog ground probe pin is inserted in the assembly block, and electrically connected to the DUT and another independent main ground.

Abstract: A testing apparatus includes a testing stage and an element pickup module. The test loader includes a testing area and a plurality of terminals arranged within the testing area. The element pickup module includes a mobile arm movable towards the testing stage, an air passage set disposed within the mobile arm and respectively connected to the vacuum pump equipment and the mobile arm, and a pressure-buffering portion. The pressure-buffering portion includes an elastic pad and a plurality of penetrating openings. The elastic pad is disposed on the bottom portion of the mobile arm, and provided with a flat surface for contacting a semiconductor element. The penetrating openings are distributed on the flat surface to connect to the air passage set so that the semiconductor element is fixedly sucked on the flat surface by the vacuum pump equipment through the penetrating openings.

Abstract: A testing system includes a testing apparatus and a crack noise monitoring device. The testing apparatus includes a testing stage and an element pickup module for pressing a semiconductor element on the testing stage. The crack noise monitoring device includes a database unit, a sound conduction set, a voiceprint generation unit and a processing unit. The database unit has a first voiceprint pattern. The sound conduction set is connected to the voiceprint generation unit and the testing apparatus for transmitting a sound wave from the semiconductor element to the voiceprint generation unit. The voiceprint generation unit receives and converts the sound wave into a second voiceprint pattern. The processing unit is electrically connected to the voiceprint generating unit and the database unit for determining whether the first voiceprint pattern is identical to the second voiceprint pattern.

Abstract: A thermal peak suppression device includes a heat dissipation fin set, a heat dissipator, a thermal phase change material, a filling gas, a fin-array frame and a capillary tube. The heat dissipator includes a thermal conductive block thermally coupled to the heat dissipation fin set, and a closed cavity formed inside the thermal conductive block to have a hot zone and a cold zone. The thermal phase change material is disposed within the hot zone. The filling gas is disposed within the cold zone. The fin-array frame is connected to the thermal conductive block within the cold zone. Two opposite ends of the capillary tube are respectively located within the cold zone and the hot zone. When the thermal phase change material is transformed into a liquid state, the thermal phase change material is sent to the hot zone through the capillary tube.