Abstract: A soft-switching power converter includes a main switch, an energy-releasing switch, and an inductive coupled unit. The main switch is a controllable switch. The energy-releasing switch is coupled to the main switch. The inductive coupled unit is coupled to the main switch and the energy-releasing switch. The inductive coupled unit includes a first inductance, a second inductance coupled to the first inductance, and an auxiliary switch unit. The auxiliary switch unit is coupled to the second inductance to form a closed loop. The main switch and the energy-releasing switch are alternately turned on and turned off. The auxiliary switch unit is controlled to start turning on before the main switch is turned on so as to provide at least one current path.

Abstract: A display panel including a circuit board, a plurality of bonding pads, a plurality of light emitting devices, and a plurality of solder patterns is provided. The bonding pads are disposed on the circuit board, and each includes a first metal layer and a second metal layer. The second metal layer is located between the first metal layer and the circuit board. The first metal layer includes an opening overlapping the second metal layer. A material of the first metal layer is different from a material of the second metal layer. The light emitting devices are electrically bonded to the bonding pads. Each of the solder patterns electrically connects one of the light emitting devices and one of the bonding pads. The solder patterns each contact the second metal layer through the opening of the first metal layer of one of the bonding pads to form a eutectic bonding.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: A display driver circuit for controlling a display panel having a plurality of light-emission diode (LED) strings includes a plurality of current regulators and a control circuit. Each of the plurality of current regulators is configured to control one of the plurality of LED strings. The control circuit, coupled to the plurality of current regulators, is configured to generate a plurality of pulses in a plurality of pulse width modulation (PWM) signals and output each of the plurality of PWM signals to a respective current regulator among the plurality of current regulators. Wherein, the plurality of pulses are scrambled.

Abstract: Disclosed is a thermal conduction-electrical conduction isolated circuit board with a ceramic substrate and a power transistor embedded, mainly comprising: a dielectric material layer, a heat-dissipating ceramic block, a securing portion, a stepped metal electrode layer, a power transistor, and a dielectric material packaging, wherein a via hole is formed in the dielectric material layer, the heat-dissipating ceramic block is correspondingly embedded in the via hole, the heat-dissipating ceramic block has a thermal conductivity higher than that of the dielectric material layer and a thickness less than that of the dielectric material layer, the stepped metal electrode layer conducts electricity and heat for the power transistor, the dielectric material packaging is configured to partially expose the source connecting pin, drain connecting pin, and gate connecting pin of the encapsulated stepped metal electrode layer.

Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

Abstract: An antiferroelectric field effect transistor (Anti-FeFET) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. The antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. This enables the antiferroelectric layer in the FeFET to provide a sharper/larger voltage drop for an erase operation of the FeFET (e.g., in which the FeFET switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.

Abstract: A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer.

Abstract: A preparation method for a circuit board connection structure includes: providing a circuit board module that including a first outer wiring layer, and the first outer wiring layer including solder pads; forming a first pyrolytic adhesive layer and an inner wiring layer on the first outer wiring layer; forming a second pyrolytic adhesive layer and a second copper foil layer on the inner wiring layer; defining a plurality of through holes each configured to expose one of the solder pads; forming a copper plating layer on the second copper foil layer; etching the copper plating layer and the second copper foil layer to form a second outer wiring layer, thereby obtaining an intermediate body; heating and washing the intermediate body to remove the first pyrolytic adhesive layer and the second pyrolytic adhesive layer. The present application also provides a circuit board connection structure.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.

Abstract: A casing structure of electronic device including a metal base plate, a transparent cathodic electrodeposition paints layer, and a transparent paints coating layer is provided. The metal base plate has brushed texture and high gloss surface. The transparent cathodic electrodeposition paints layer is disposed on the base metal base plate. The transparent paints coating layer is disposed on the transparent cathodic electrodeposition paints layer. A manufacturing method of casing structure of electronic device is also provided.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

Abstract: A display, including a carrying main body, a flexible carrier film, a double-sided tape, and an adhesive layer, is provided. The flexible carrier film includes a first bonding section and a second bonding section respectively disposed on two opposite sides of the carrying main body, and a bending section connected between the first bonding section and the second bonding section. The flexible carrier film has an inner surface and an outer surface opposite to each other. The inner surface has at least one first groove at the bending section. The flexible carrier film has a display layer thereon. At least a part of the display layer is connected to the outer surface at the second bonding section. The double-sided tape is disposed between the first bonding section and the carrying main body. The adhesive layer is disposed between the inner surface and the carrying main body at the bending section.

Abstract: A flexible display module includes a first light-transmissive layer and a first display layer. The first light-transmissive layer includes a display surface. The first light-transmissive layer has a first width in a second direction. The first display layer is disposed below the first light-transmissive layer. The first display layer has a second width in the second direction. The first display layer includes a circuit layer. The flexible display module is configured to be bent along an axis, the axis extends along a first direction, the first direction is perpendicular to the second direction, and the first width is greater than the second width. A line width of the circuit layer more close to a periphery of the display surface is less than a line width of the circuit layer more close to an inner area of the display surface.

Abstract: A casting structure allowing inlayed inner and outer member to be viewed includes: at least one inner member, formed as a three-dimensional shape; an outer member, formed with an inlaying space for allowing the inner member to be combined and inlayed therein, wherein the outer member is a three-dimensional shape formed through a material capable being viewed through; and a filling material member, made of a material capable of being viewed through and filled at an outer side of the outer member inlayed with the inner member so as to form a casting member; wherein, with the inner member being inlayed in the outer member, the filling material member is able to enclose and to be processed with a casting operation for forming the casting member capable of being viewed through.

Abstract: An object forming structure includes: at least two first original images, respectively provided with different vectors, and extended for forming at least two first original image three-dimensional shapes; at least one intersect fixed point, extended with at least one intersect direction through the intersect fixed point, wherein at least two second image three-dimensional shapes are formed through the first original image three-dimensional shapes being extended; and at least two third image three-dimensional shapes, stacked with the at least two second image three-dimensional shapes, wherein a Boolean function is utilized for confirming a selected desired zone for forming a new object formation; wherein, the new object formation formed via the third image three-dimensional shapes is obtained through a combination of intersect or union or equalize the different vectors, the first original image three-dimensional shapes are presented via the corresponding vectors for presenting different shapes in other angles.