Patents by Inventor Chih-Chieh Shao

Chih-Chieh Shao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DATA ANALYSIS SYSTEM AND DATA ANALYSIS METHOD
    Publication number: 20210349862
    Abstract: A data analysis method includes steps of: obtaining at least one data table; wherein the data table includes a plurality of fields, and each of the fields stores field data; analyzing the field type according to the field data; determining a field category for each of the fields; calculating the similarity between the fields in different tables; determining the correlation between each of the fields according to the similarity; generating a field data description file according to the field type, the field categories and the correlations; and determining whether the field data description file is abnormal. A data analysis system is also disclosed.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 11, 2021
    Inventors: Chih-Chieh SHAO, Zheng-Bang LIU, Ju-Hsin KUNG
  • Test pad design for reducing the effect of contact resistances
    Patent number: 7825678
    Abstract: An integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and connected to the integrated circuit devices. Test pads are grouped in pairs, with the test pads in a same pair are interconnected.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: November 2, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yih-Yuh Doong, Tseng Chin Lo, Chien-Chang Lee, Chih-Chieh Shao
  • Test Pad Design for Reducing the Effect of Contact Resistances
    Publication number: 20100045325
    Abstract: An integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and connected to the integrated circuit devices. Test pads are grouped in pairs, with the test pads in a same pair are interconnected.
    Type: Application
    Filed: August 22, 2008
    Publication date: February 25, 2010
    Inventors: Yih-Yuh Doong, Tseng Chin Lo, Chien-Chang Lee, Chih-Chieh Shao