Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a first source/drain region disposed under a well portion, a second source/drain region disposed adjacent the first source/drain region, a dielectric material disposed between the first and second source/drain regions, and a conductive contact having a first portion disposed under the first source/drain region and a second portion disposed adjacent the first source/drain region. The second portion is disposed in the dielectric material. The structure further includes a conductive feature disposed in the dielectric material, and the conductive feature is electrically connected to the conductive contact. The conductive feature has a top surface that is substantially coplanar with a top surface of the well portion.

Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a fin disposed in a first region of the semiconductor device, channel members disposed in a second region of the semiconductor device and stacked in a vertical direction, first and second metal gates disposed on a top surface of the fin, a third metal gate wrapping around each of the channel members, a first implant region in the fin with a first conductivity type, and a second implant region in the fin with a second conductivity opposite the first conductivity type. The fin includes first and second type epitaxial layers alternatingly disposed in the vertical direction. The first and second type epitaxial layers have different material compositions. The first type epitaxial layers and the channel members have the same material composition.

Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Abstract: The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.

Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.

Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.

Abstract: A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first channel structure and a second channel structure over a substrate. The semiconductor device structure also includes a first gate stack over the first channel structure, and the first gate stack has a first width. The semiconductor device structure further includes a second gate stack over the second channel structure. The second gate stack has a protruding portion extending away from the second channel structures. The protruding portion of the second gate stack has a second width, and half of the first width is greater than the second width.

Abstract: A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

Abstract: A polish pad replacing apparatus includes a polish spindle loaded with a first polish pad, a first roller movable reciprocally under the polish spindle, a clamping element and a position sensor. The clamping element, disposed at the first roller, is to clamp or release the first polish pad. In replacing the first polish pad, a controller moves the polish spindle to a replacing position, the position sensor detects the polish spindle and if positive, have the controller to moves the first roller to insert the clamping element between the polish spindle and the first polish pad so as to clamp an edge of the first polish pad, the first roller is then moved to peel the first polish pad off, and then the first roller is moved to paste a second polish pad onto the polish spindle.

Abstract: A display apparatus is disclosed. The display apparatus includes a color filter, a first backlight unit, a second backlight unit and a third backlight unit. The first backlight unit, the second backlight unit and the third backlight unit are disposed relative to the color filter and independently emit a first color light, a second color light and a third color light to the color filter respectively. In a brightness mode, the first color light has a first intensity, the second color light has a second intensity and the third color light has a third intensity. In a color mode, when a display image of the display apparatus is biased to a third color corresponding to the third color light, the display apparatus reduces at least one of the first intensity and the second intensity.

Abstract: A backlight module provides light to a display panel and includes a bottom board, a support frame, first and second magnetic members, a light guide device, and a light source. The support frame is connected to the bottom board to contain the light guide device. The light source is disposed on the bottom board corresponding to a light entrance surface of the light guide device. Light of the light source is incident into the light guide device via the light entrance surface and emitted to the display panel from a light exit surface of the light guide device. The first magnetic member is disposed on the support frame or the light guide device corresponding to the light source. The second magnetic member is disposed corresponding to the first magnetic member to generate a magnetic force for driving the light entrance surface to be aligned with the light source.

Abstract: A display apparatus is disclosed. The display apparatus includes a color filter, a first backlight unit, a second backlight unit and a third backlight unit. The first backlight unit, the second backlight unit and the third backlight unit are disposed relative to the color filter and independently emit a first color light, a second color light and a third color light to the color filter respectively. In a brightness mode, the first color light has a first intensity, the second color light has a second intensity and the third color light has a third intensity. In a color mode, when a display image of the display apparatus is biased to a third color corresponding to the third color light, the display apparatus reduces at least one of the first intensity and the second intensity.

Abstract: A display panel formed by connecting a plurality of panels, includes a first substrate, a plurality of first light-emitting elements, a first patterned conductive layer and a first driving circuit device. The first substrate has a first light output surface and a first sidewall, wherein the first sidewall connects to the first light output surface, and forms a non-180° angle with the first light output surface. The first light-emitting elements are disposed on the first light output surface. The first patterned conductive layer is disposed on the first sidewall. The first driving circuit device is disposed on the first substrate, adjacent to an edge of the first substrate and electrically connected to one of the first light-emitting elements.

Abstract: A display panel includes a first substrate used to connect with at least one other substrate, a plurality of first light-emitting elements and a first patterned conductive layer. The first substrate includes a first light output surface and a first sidewall connecting to the first light output surface, wherein the first sidewall forms a non-180° angle with the first light output surface. The plurality of first light-emitting elements are disposed on the first light output surface. The first patterned conductive layer is disposed on the first sidewall.

Abstract: A display device including a display panel, a light guide plate and a light emitting module is disclosed. The light guide plate is opposite to the display panel and has a light incident surface. The light emitting module emits a light to the light incident surface. The light emitting module includes a substrate, multiple first light emitting elements and multiple second light emitting elements. The first light emitting elements are disposed on the substrate along the first direction and divided into multiple first luminous areas. Each first luminous area includes at least two first light emitting elements. The second light emitting elements are disposed on the substrate along the first direction and divided into multiple second luminous areas. Each second luminous area includes at least two second light emitting elements. The first and second luminous areas are staggered along the second direction perpendicular to the first direction.