Abstract: A method includes receiving a substrate having a front side and a back side, forming a shallow trench in the substrate from the front side, forming a liner layer including a first dielectric material in the shallow trench, depositing a second dielectric material different from the first dielectric material on the liner layer to form an isolation feature in the shallow trench, forming an active region surrounded by the isolation feature, forming a gate stack on the active region, forming a source/drain (S/D) feature on the active region and on a side of the gate stack, thinning down the substrate from the back side such that the isolation feature is exposed, etching the active region to expose the S/D feature from the back side to form a backside trench, and forming a backside via feature landing on the S/D feature and surrounded by the liner layer.

Abstract: A semiconductor device and a method of manufacturing thereof are provided. The method comprises: forming a gate electrode over a substrate; forming source/drain regions beside the gate electrode; forming contact plugs on the source/drain regions; forming a dielectric layer over the contact plugs and the gate electrode; forming first openings and a second opening in the dielectric layer to expose portions of the contact plugs and a portion of the gate electrode respectively; performing a pre-clean process such as applying an ozone-containing source to the exposed portions of the contact plugs and the gate electrode; performing a surface treatment to the first and second openings to passivate sidewalls of the first and second openings; forming a conductive layer to fill the first openings and the second opening in a same deposition process by using a same metal precursor; and performing a planarization process.

Abstract: An integrated circuit includes a substrate at a front side of the integrated circuit. A first gate all around transistor is disposed on the substrate. The first gate all around transistor includes a channel region including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the channel region, and a gate electrode. A shallow trench isolation region extends into the integrated circuit from the backside. A backside gate plug extends into the integrated circuit from the backside and contacts the gate electrode of the first gate all around transistor. The backside gate plug laterally contacts the shallow trench isolation region at the backside of the integrated circuit.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple first semiconductor nanostructures over a substrate and multiple second semiconductor nanostructures over the substrate. The semiconductor device structure also includes a dielectric structure between the first semiconductor nanostructures and the second semiconductor nanostructures. The semiconductor device structure further includes a metal gate stack wrapped around the first semiconductor nanostructures and the second semiconductor nanostructures. The metal gate stack has a gate dielectric layer and a gate electrode. The gate dielectric layer extends along a sidewall of a lower portion of the dielectric structure. A topmost surface of the gate dielectric layer is between a topmost surface of the first semiconductor nanostructures and a topmost surface of the dielectric structure.

Abstract: The present disclosure describes a semiconductor device having a dielectric structure between a source/drain (S/D) structure and a contact structure. The semiconductor device includes a S/D structure on a substrate, a dielectric structure on a top surface of the S/D structure, and a S/D contact structure on the S/D structure and the dielectric structure. A portion of the S/D contact structure is in contact with a top surface of the dielectric structure.

Abstract: An embodiment is a device including a first die and a substrate including a first surface and a second surface opposite the first surface. The device also includes an active device on the first surface of the substrate. The device also includes a first interconnect structure on the first surface of the substrate. The device also includes a through substrate via extending through the first interconnect structure and the substrate to the second surface of the substrate, the through substrate via being electrically coupled to metallization patterns in the first interconnect structure. The device also includes one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the through substrate via.

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

Abstract: The disclosure provides a converter circuit, a power stage circuit and a temperature balancing method. The converter circuit includes power stage circuits and a control circuit. The power stage circuit includes a power circuit, a temperature sense circuit, a current sense circuit and a current feedback control circuit. The temperature sense circuit senses a temperature of the power stage circuit, to output a temperature sense value. The current sense circuit senses an output current of the power circuit, to output a current sense value. The current feedback control circuit compares the temperature sense value with a highest temperature value of the power stage circuits, and outputs one of the current sense value and adjusted current sense value to the control circuit according to a comparison result of the temperature sense value and the highest temperature value.

Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain epitaxial features; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside; and a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.

Abstract: Embodiments of the present disclosure provide a method for forming backside gate contacts and semiconductor fabricated thereof. A semiconductor device includes both signal outputs, such as source/drain contacts, and signal inputs, such as gate contacts, formed on a backside of the substrate. The backside gate contacts and backside source/drain contacts are formed in a self-aligned manner.

Abstract: An integrated circuit includes a substrate having a semiconductor layer. The integrated circuit includes a transistor. The transistor includes stacked channels above the semiconductor layer, a first source/drain region in contact with the channels, and a second source/drain region in contact with the channels. A backside source/drain contact is positioned in the substrate directly below and electrically coupled to the first source/drain region. A frontside source/drain contact is directly above and electrically coupled to the first source/drain region. A bottom semiconductor structure is positioned below the second source/drain region and in contact with the semiconductor layer.

Abstract: A semiconductor device may include one or more transistor structures that include a plurality of source/drain regions and a gate structure between the source/drain regions. The semiconductor device may further include one or more dielectric layers between a source/drain contact structure and a gate structure of the one or more of the transistor structures. The one or more dielectric layers may be manufactured using on oxidation treatment process to tune the dielectric constant of the one or more dielectric layers. The dielectric constant of the one or more dielectric layers may be tuned to reduce the parasitic capacitance between the source/drain contact structure and the gate structure (which are conductive structures). In particular, the dielectric constant of the one or more spacer dielectric may be tuned using the oxidation treatment process to lower the as-deposited dielectric constant of the one or more dielectric layers.

Abstract: An integrated circuit includes a substrate at a front side of the integrated circuit. A first gate all around transistor is disposed on the substrate. The first gate all around transistor includes a channel region including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the channel region, and a gate electrode. A shallow trench isolation region extends into the integrated circuit from the backside. A backside gate plug extends into the integrated circuit from the backside and contacts the gate electrode of the first gate all around transistor. The backside gate plug laterally contacts the shallow trench isolation region at the backside of the integrated circuit.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.

Abstract: A voltage conversion system includes a multi-phase voltage converter and a controller. The multi-phase voltage converter is coupled to a load. A first phase circuit, a second phase circuit, and a third phase circuit in the multi-phase voltage converter enter a charging state in sequence during a first period. At least one driver circuit in the multi-phase voltage converter is coupled to the first phase circuit, the second phase circuit, and the third phase circuit. The controller is coupled to the at least one driver circuit. According to a trigger event, the controller outputs at least one driving signal to the at least one driver circuit such that the at least one driver circuit adjusts the second phase circuit or the third phase circuit to be an activation item with highest priority during a second period after the first period.

Abstract: A polish pad replacing apparatus includes a polish spindle loaded with a first polish pad, a first roller movable reciprocally under the polish spindle, a clamping element and a position sensor. The clamping element, disposed at the first roller, is to clamp or release the first polish pad. In replacing the first polish pad, a controller moves the polish spindle to a replacing position, the position sensor detects the polish spindle and if positive, have the controller to moves the first roller to insert the clamping element between the polish spindle and the first polish pad so as to clamp an edge of the first polish pad, the first roller is then moved to peel the first polish pad off, and then the first roller is moved to paste a second polish pad onto the polish spindle.

Abstract: A display apparatus is disclosed. The display apparatus includes a color filter, a first backlight unit, a second backlight unit and a third backlight unit. The first backlight unit, the second backlight unit and the third backlight unit are disposed relative to the color filter and independently emit a first color light, a second color light and a third color light to the color filter respectively. In a brightness mode, the first color light has a first intensity, the second color light has a second intensity and the third color light has a third intensity. In a color mode, when a display image of the display apparatus is biased to a third color corresponding to the third color light, the display apparatus reduces at least one of the first intensity and the second intensity.

Abstract: A backlight module provides light to a display panel and includes a bottom board, a support frame, first and second magnetic members, a light guide device, and a light source. The support frame is connected to the bottom board to contain the light guide device. The light source is disposed on the bottom board corresponding to a light entrance surface of the light guide device. Light of the light source is incident into the light guide device via the light entrance surface and emitted to the display panel from a light exit surface of the light guide device. The first magnetic member is disposed on the support frame or the light guide device corresponding to the light source. The second magnetic member is disposed corresponding to the first magnetic member to generate a magnetic force for driving the light entrance surface to be aligned with the light source.

Abstract: A display apparatus is disclosed. The display apparatus includes a color filter, a first backlight unit, a second backlight unit and a third backlight unit. The first backlight unit, the second backlight unit and the third backlight unit are disposed relative to the color filter and independently emit a first color light, a second color light and a third color light to the color filter respectively. In a brightness mode, the first color light has a first intensity, the second color light has a second intensity and the third color light has a third intensity. In a color mode, when a display image of the display apparatus is biased to a third color corresponding to the third color light, the display apparatus reduces at least one of the first intensity and the second intensity.

Abstract: A display panel formed by connecting a plurality of panels, includes a first substrate, a plurality of first light-emitting elements, a first patterned conductive layer and a first driving circuit device. The first substrate has a first light output surface and a first sidewall, wherein the first sidewall connects to the first light output surface, and forms a non-180° angle with the first light output surface. The first light-emitting elements are disposed on the first light output surface. The first patterned conductive layer is disposed on the first sidewall. The first driving circuit device is disposed on the first substrate, adjacent to an edge of the first substrate and electrically connected to one of the first light-emitting elements.