Patents by Inventor Chih-Chieh Wang

Chih-Chieh Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11616143
    Abstract: Embodiments of the present disclosure provide a method for forming backside metal contacts with reduced Cgd and increased speed. Particularly, source/drain features on the drain side, or source/drain features without backside metal contact, are recessed from the backside to the level of the inner spacer to reduce Cgd. Some embodiments of the present disclosure use a sacrificial liner to protect backside alignment feature during backside processing, thus, preventing shape erosion of metal conducts and improving device performance.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yuan Chen, Huan-Chieh Su, Pei-Yu Wang, Chih-Hao Wang
  • Publication number: 20230083007
    Abstract: An electronic device and a method for manufacturing a flexible circuit board are provided. The electronic device includes the flexible circuit board. The flexible circuit board includes a first flexible substrate, a first seed layer, a first conductive layer, and a second seed layer. The first seed layer is disposed on the first flexible substrate. The first conductive layer is disposed on the first seed layer. The second seed layer is disposed on the first conductive layer. The first seed layer is in contact with the first conductive layer.
    Type: Application
    Filed: November 17, 2022
    Publication date: March 16, 2023
    Applicant: Innolux Corporation
    Inventors: Jia Sin Li, Tong-Jung Wang, Chia-Chieh Fan, Shan Shan Hsu, Chih Han Ma
  • Patent number: 11605622
    Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: March 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.
    Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chuei-Tang Wang, Hsing-Kuo Hsia, Chen-Hua Yu
  • Publication number: 20230071615
    Abstract: A floating electrical connector includes a housing with a tubular portion. An axis is defined in a center of the tubular portion. Several floating terminals are arranged around the axis and are partially connected. Each floating terminal has an inner terminal sheet on an inner side and a spring structure on an outer side. Each spring structure is connected to one of the inner terminal sheets. A portion of the inner terminal sheet is inserted into the tubular portion and arranged along an inner peripheral surface of the tubular portion. The portion of each inner terminal sheet located in the tubular portion has an electronic contact bulging inward. Several external pins are electrically connected around the floating terminals. When a conductive pin is inserted into the tubular portion, the spring structures could elastically deform, allowing the tubular portion to adapt to a horizontal deviation or a skew deviation of the conductive pin, providing a greater tolerance for alignment deviations.
    Type: Application
    Filed: March 14, 2022
    Publication date: March 9, 2023
    Applicant: ALPHA NETWORKS INC.
    Inventors: CHIH-KUANG WANG, YING-CHIEH SHIH, I-FENG LO, CHIN-CHIH CHUANG
  • Publication number: 20230075343
    Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.
    Type: Application
    Filed: November 14, 2022
    Publication date: March 9, 2023
    Inventors: Li-Zhen YU, Huan-Chieh SU, Shih-Chuan CHIU, Lin-Yu HUANG, Cheng-Chi CHUANG, Chih-Hao WANG
  • Publication number: 20230071502
    Abstract: A dual-band transform circuit structure includes a first transmission line, a second transmission line, and a conductive layer. The first transmission line has a first input terminal, a first output terminal, and a second output terminal. The second transmission line has a second input terminal, a third input terminal, a third output terminal, and a fourth output terminal. The second input terminal is coupled to the first output terminal, and the third input terminal is coupled to the second output terminal. The conductive layer is stacked with the first transmission and the second transmission line. The conductive layer includes a first hollow pattern. The first hollow pattern and the second transmission line are overlapped in a top view.
    Type: Application
    Filed: September 7, 2022
    Publication date: March 9, 2023
    Inventors: TZU-HAO HSIEH, CHIH-CHIEH WANG
  • Patent number: 11600543
    Abstract: A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: March 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Chieh Chen, Chih-Ren Hsieh, Ming-Lun Lee, Wei-Ming Wang, Ming Chyi Liu
  • Publication number: 20230069501
    Abstract: A method includes providing a first semiconductor layer at a frontside of a structure; implanting first dopants of a first conductivity-type into the first semiconductor layer, resulting in a doped layer in the first semiconductor layer; forming a stack of semiconductor layers over the first semiconductor layer; patterning the stack of semiconductor layers and the first semiconductor layer into fins; forming an isolation structure adjacent to a lower portion of the fins; etching the stack of semiconductor layers to form a source/drain trench over the first semiconductor layer; forming a source/drain feature in the source/drain trench, wherein the source/drain feature is doped with second dopants of a second conductivity-type opposite to the first conductivity-type; forming a contact hole at a backside of the structure, wherein the contact hole exposes the doped layer in the first semiconductor layer; and forming a first contact structure in the contact hole.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Chih Chieh Yeh, Ming-Shuan Li, Chih-Hung Wang, Zi-Ang Su
  • Publication number: 20230057702
    Abstract: Semiconductor device includes light-emitting die and semiconductor package. Light emitting die includes substrate and first conductive pad. Substrate has emission region located at side surface. First conductive pad is located at bottom surface of substrate. Semiconductor package includes semiconductor-on-insulator substrate, interconnection structure, second conductive pad, and through semiconductor via. Semiconductor-on-insulator substrate has linear waveguide formed therein. Interconnection structure is disposed on semiconductor-on-insulator substrate. Edge coupler is embedded within interconnection structure and is connected to linear waveguide. Semiconductor-on-insulator substrate and interconnection structure include recess in which light-emitting die is disposed. Edge coupler is located close to sidewall of recess. Second conductive pad is located at bottom of recess. Through semiconductor via extends across semiconductor-on-insulator substrate to contact second conductive pad.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Patent number: 11588050
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes an epitaxial source feature and an epitaxial drain feature, a vertical stack of channel members disposed over a backside dielectric layer, the vertical stack of channel members extending between the epitaxial source feature and the epitaxial drain feature along a direction, a gate structure wrapping around each of the vertical stack of channel members, and a backside source contact disposed in the backside dielectric layer. The backside source contact includes a top portion adjacent the epitaxial source feature and a bottom portion away from the epitaxial source feature. The top portion and the bottom portion includes a step width change along the direction.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: February 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20230047194
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure also includes a gate structure including a first portion wrapping around the first nanostructures and a second portion wrapping around the second nanostructures. The semiconductor structure also includes a dielectric feature sandwiched between the first portion and the second portion of the gate structure. In addition, the dielectric feature includes a bottom portion and a top portion over the bottom portion, and the top portion of the dielectric feature includes a shell layer and a core portion surrounded by the shell layer.
    Type: Application
    Filed: March 16, 2022
    Publication date: February 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Li-Zhen YU, Lo-Heng CHANG, Cheng-Chi CHUANG, Chih-Hao WANG
  • Publication number: 20230050249
    Abstract: A semiconductor device includes a first gate structure and a second gate structure over a fin, a dielectric cut pattern sandwiched by the first and second gate structures, and a liner layer surrounding the dielectric cut pattern. The dielectric cut pattern is spaced apart from the fin and extends further from the substrate than a first gate electrode of the first gate structure and a second gate electrode of the second gate structure. The semiconductor device further includes a conductive feature sandwiched by the first and second gate structures. The conductive feature is divided by the conductive feature into a first segment and a second segment. The first segment of the conductive feature is above a source/drain region of the fin.
    Type: Application
    Filed: April 26, 2022
    Publication date: February 16, 2023
    Inventors: Lin-Yu HUANG, Li-Zhen Yu, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
  • Patent number: 11581224
    Abstract: A method of forming a semiconductor transistor device. The method comprises forming a fin-shaped channel structure over a substrate and forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite endings of the fin structure. The method further comprises forming a metal gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain epitaxial structure and the second source/drain epitaxial structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang, Zhi-Chang Lin, Li-Zhen Yu
  • Patent number: 11580621
    Abstract: Aspects of the disclosure provide a device for processing frames with aliasing artifacts. For example, the device can include a motion estimation circuit, a warping circuit coupled to the motion estimation circuit, and a temporal decision circuit coupled to the warping circuit. The motion estimation circuit can estimate a motion value between a current frame and a previous frame. The warping circuit can warp the previous frame based on the motion value such that the warped previous frame is aligned with the current frame and determine whether the current frame and the warped previous frame are consistent. The temporal decision circuit can generate an output frame, the output frame including either the current frame and the warped previous frame when the current frame and the warped previous frame are consistent, or the current frame when the current frame and the warped previous frame are not consistent.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: February 14, 2023
    Assignee: MEDIATEK INC.
    Inventors: Jen Cheng Lung, Pei-Kuei Tsung, Chih-Wei Chen, Yao-Sheng Wang, Shih-Che Chen, Yu-Sheng Lin, Chih-Wen Goo, Shih-Chin Lin, Huang Tsung-Shian, Ying-Chieh Chen
  • Publication number: 20230043669
    Abstract: A method of manufacturing an integrated circuit device including a self-aligned air spacer including the operations of forming a dummy gate, forming a sidewall on the dummy gate, forming a dummy layer on the sidewall, constructing a gate structure within an opening defined by the sidewall, removing at least a portion of the first dummy layer to form a first recess between the sidewall layer and the dummy gate, and capping the first recess to form a first air spacer.
    Type: Application
    Filed: August 5, 2021
    Publication date: February 9, 2023
    Inventors: Huan-Chieh SU, Jia-Chuan YOU, Cheng-Chi CHUANG, Chih-Hao WANG
  • Publication number: 20230039440
    Abstract: A device includes a substrate. A channel region of a transistor overlies the substrate and a source/drain region is in contact with the channel region. The source/drain region is adjacent to the channel region along a first direction. A source/drain contact is disposed on the source/drain region. A gate electrode is disposed on the channel region and a gate contact is disposed on the gate electrode. A first low-k dielectric layer is disposed between the gate contact and the source/drain contact along the first direction.
    Type: Application
    Filed: March 15, 2022
    Publication date: February 9, 2023
    Inventors: Meng-Huan JAO, Huan-Chieh SU, Yi-Bo LIAO, Cheng-Chi CHUANG, Jin CAI, Chih-Hao WANG
  • Publication number: 20230034360
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first gate stack wrapping around first nanostructures, a second gate stack wrapping around second nanostructures, a gate isolation structure interposing between the first gate stack and the second gate stack, a first source/drain feature adjoining the first nanostructures, a second source/drain feature adjoining the second nanostructures, and a source/drain spacer structure interposing between the first source/drain feature and the second source/drain feature. The gate isolation structure covers a sidewall of the source/drain spacer structure.
    Type: Application
    Filed: February 15, 2022
    Publication date: February 2, 2023
    Inventors: Huan-Chieh Su, Zhi-Chang Lin, Li-Zhen Yu, Chun-Yuan Chen, Lo-Heng Chang, Cheng-Chi Chuang, Chih-Hao Wang, Lin-Yu Huang
  • Publication number: 20230036677
    Abstract: The present invention is a method for controlling a Davinci surgical device. Firstly, controlling an operation part of a remote operation device to enter the inner of a body for executing a surgical operation. Then, an image capturing unit captures a plurality of corresponding surgical images to a control device, and the control device obtains a first torque component, a second torque component and an element action of the remote surgical device according to the surgical images to operate an output strength of the remote surgical device for further generating corresponding strength feedback by the output strength. Thus, the user can get the control status of the remote surgical device to prevent accidental iatrogenic injury from over-force and to proceed with the operation with improved accuracy.
    Type: Application
    Filed: September 22, 2021
    Publication date: February 2, 2023
    Inventors: PO-YUN LIU, HSIEN-CHE CHUANG, CHIH-CHENG CHIEN, YEN-CHIEH WANG
  • Patent number: 11555981
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: January 17, 2023
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Patent number: D979562
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: February 28, 2023
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Po-Yang Chien, Hao-Jen Fang, Wei-Yi Chang, Chun-Chieh Chen, Chen-Cheng Wang, Chih-Wen Chiang, Sheng-Hung Lee