Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a base structure. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure sandwiching the channel structures. The semiconductor device structure further includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. In addition, the semiconductor device structure includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.

Abstract: Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.

Abstract: The present disclosure describes a method to form a backside power rail (BPR) semiconductor device with an air gap. The method includes forming a fin structure on a first side of a substrate, forming a source/drain (S/D) region adjacent to the fin structure, forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region, and forming a capping structure on the first S/D contact structure. The method further includes removing a portion of the first S/D contact structure through the capping structure to form an air gap and forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region. The second side is opposite to the first side.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.

Abstract: Disclosed is a thermal conduction-electrical conduction isolated circuit board with a ceramic substrate and a power transistor embedded, mainly comprising: a dielectric material layer, a heat-dissipating ceramic block, a securing portion, a stepped metal electrode layer, a power transistor, and a dielectric material packaging, wherein a via hole is formed in the dielectric material layer, the heat-dissipating ceramic block is correspondingly embedded in the via hole, the heat-dissipating ceramic block has a thermal conductivity higher than that of the dielectric material layer and a thickness less than that of the dielectric material layer, the stepped metal electrode layer conducts electricity and heat for the power transistor, the dielectric material packaging is configured to partially expose the source connecting pin, drain connecting pin, and gate connecting pin of the encapsulated stepped metal electrode layer.

Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.

Abstract: A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.

Abstract: A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

Abstract: The invention encompasses hydrogels, monomer precursors of the hydrogels, methods for the preparation thereof, and methods of use therefor. The linking of monomers can take place using non-radical, bioorthogonal reactions such as copper-free click-chemistry.

Abstract: The invention, in some aspects relates to compositions and methods for imaging biological systems and physiological activity and conditions in cells.

Abstract: The invention encompasses hydrogels, monomer precursors of the hydrogels, methods for the preparation thereof, and methods of use therefor. The linking of monomers can take place using non-radical, bioorthogonal reactions such as copper-free click-chemistry.

Abstract: The invention provides a method termed protein retention ExM (proExM), in which proteins, rather than labels, are anchored to the swellable gel, using a cross-linking molecule. This proExM strategy can be used to perform nanoscale imaging of immunostained cells and tissues as well as samples expressing various FPs as fluorescent signals from genetically encoded fluorescent proteins and/or conventional fluorescently labeled secondary antibodies and streptavidin that are directly anchored to the gel are preserved even when subjected to the nonspecific proteolytic digestion.

Abstract: An image module and an electronic device using the same are provided. The image module includes a connecting element and a lens structure. The connecting element includes an inner ring, an outer ring and a connecting portion. The connecting portion connects the inner ring and the outer ring. The lens structure is mounted in the inner ring.

Abstract: A crystal growth apparatus includes a crucible, a heating device, a thermal insulation cover, and a driving device. The crucible contains materials to be melted, wherein the heating device heats the crucible to melt the materials; the thermal insulation cover is provided upon the materials, wherein the thermal insulation cover includes a main body, which has a bottom surface facing an interior of the crucible, and a insulating member being provided at the main body; the driving device moves the thermal insulation cover towards or away from the materials, whereby, the thermal insulation cover effectively blocks heat conduction and heat convection, which prevents thermal energy from escaping out of the crucible.

Abstract: A stirring apparatus of an ingot casting furnace includes a rotating shaft and at least one fin. The fin is provided onto the rotating shaft, and has a first edge, a second edge of unequal length provided correspondingly, and a third edge connecting the first and the second edges. The rotating shaft can be driven to rotate, which consequently drives the at least one fin to stir materials in a crucible. The length of the first edge is different from that of the second edge in order for the materials in the crucible can be mixed with dopants more uniformly during the stirring process to produce ingots of stable quality.

Abstract: The invention provides a method termed protein retention ExM (proExM), in which proteins, rather than labels, are anchored to the swellable gel, using a cross-linking molecule. This proExM strategy can be used to perform nanoscale imaging of immunostained cells and tissues as well as samples expressing various FPs as fluorescent signals from genetically encoded fluorescent proteins and/or conventional fluorescently labeled secondary antibodies and streptavidin that are directly anchored to the gel are preserved even when subjected to the nonspecific proteolytic digestion.

Abstract: The invention, in some aspects relates to compositions and methods for imaging biological systems and physiological activity and conditions in cells.

Abstract: A plasma enhanced atomic layer deposition (PEALD) system used to form thin films on substrates includes a plasma chamber, a processing chamber, two or more ring units and a control piece. The plasma chamber includes an outer and an inner quartz tubular units, whose central axes are aligned with each other. Therefore, plasma is held and concentrated in an annular space formed between the outer and outer quartz tubular units. Due to the first and second through holes, the plasma flow may be more evenly distributed on most of the surface of the substrate to form evenly distributed thin films and nano particles on the substrate. In addition, due to the alignment and misalignment between the first and second through holes, the plasma generated in the plasma chamber may be swiftly allowed or disallowed to enter to the processing chamber to prevent the precursor from forming a CVD.