Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall. The structure also includes a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type. The structure further includes a gate bridge contact disposed on the first dielectric wall, and a gate via contact disposed on the gate bridge contact.

Abstract: A method of making a semiconductor device includes etching an insulating layer to form a first opening and a second opening. The method further includes depositing a conductive material in the first opening. The method further includes performing a surface modification process on the conductive material. The method further includes depositing, after the surface modification process, a first liner layer in the second opening, wherein the first liner layer extends over the conductive material and the insulating layer. The method further includes depositing a conductive fill over the first liner layer, wherein the conductive fill includes a different material from the conductive material.

Abstract: A data transmission system and method thereof for edge computing are provided. A terminal mobile station international subscriber directory number (MSISDN) and a terminal IP of a target terminal are obtained with a domain name system (DNS) by a device providing communication services from the data transmission system. After data packets are sent to the data transmission system, if the target terminal is in an idle mode, a paging message is sent by a terminal wake-up module to enable the target terminal to return to a connected mode for communication. Before a connection is established between the data transmission system and the target terminal, downlink data packets can be temporarily stored, and the packets can be sent after the target terminal is in the connected mode. A computer readable medium for executing the data transmission method is also provided.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a first base portion and a second base portion, an isolation feature sandwiched between the first base portion and the second base portion, a center dielectric fin over the isolation feature, a first anti-punch-through (APT) feature over the first base portion, a second APT feature over the second base portion, a first stack of channel members over the first APT feature, and a second stack of channel members over the second APT feature. The center dielectric fin is sandwiched between the first stack of channel members and the second stack of channel members as well as between the first APT feature and the second APT feature.

Abstract: A circuit board includes a substrate, a build-up circuit structure, a graphene oxide layer, a graphene layer, and an insulating material layer. The build-up circuit structure is disposed on the substrate, including at least one inner circuit, at least one dielectric layer, an outer circuit, and multiple conductive vias. The dielectric layer is disposed on the inner circuit. The outer circuit is disposed on the dielectric layer. The conductive vias penetrate the dielectric layer and electrically connect the inner circuit and the outer circuit. The graphene oxide layer and the graphene layer are disposed on the build-up circuit structure at an interval. The graphene oxide layer and the graphene layer are respectively disposed in correspondence to the dielectric layer and the outer circuit. The insulating material layer is disposed on the graphene oxide layer and the graphene layer. The insulating material layer has an opening, which exposes the graphene layer.

Abstract: A top-opening substrate carrier comprises a container body, a door member and at least one latching mechanism. The latching mechanism includes a rotary drive member, a first driven cam, a second driven cam, a first connecting rod, a second connecting rod, two longitudinal latching arms and two lateral latching arms. The first driven cam and the second driven cam are disposed at two sides of the rotary drive member. When the rotary drive member is rotated by force, it links and activates the first connecting rod and the second connecting rod to synchronously drive the first driven cam and the second driven cam to rotate, thereby driving the two longitudinal latching arms and the two lateral latching arms to project towards locking holes of the container body and locked, or retract from the locking holes of the container body and unlocked.

Abstract: A method includes forming a dummy gate structure across a fin, in which the dummy gate structure has a dummy gate dielectric layer and a dummy gate electrode, forming gate spacers on sidewalls of the dummy gate structure, forming source/drain epitaxial structures on sides of the dummy gate structure, performing a first etch process to the dummy gate electrode such that a recessed dummy gate electrode remains over the fin, performing a second etch process to the gate spacers such that recessed gate spacers remain over the sidewalls of the dummy gate structure, removing the recessed dummy gate electrode and the dummy gate dielectric layer after the second etch process to form a recess between the recessed gate spacers, forming a gate structure overfilling the recess, and performing a third etch process to the gate structure such that a recessed gate structure remains between the recessed gate spacers.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, a first oxide layer, a field plate, and a second oxide layer. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure respectively. The first oxide layer includes a first portion disposed between the gate structure and the semiconductor substrate and a second portion disposed between the gate structure and the drain region. The field plate is partly disposed above the gate structure and partly disposed above the second portion of the first oxide layer. The second oxide layer includes a first portion disposed between the field plate and the gate structure and a second portion disposed between the field plate and the second portion of the first oxide layer.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The method includes forming a first dielectric feature between first and the second fin structures, wherein each first and second fin structure includes first semiconductor layers and second semiconductor layers alternatingly stacked and in contact with the first dielectric layer. The method also includes removing the second semiconductor layers so that the first semiconductor layers of the first and second fin structures extend laterally from a first side and a second side of the first dielectric feature, respectively, trimming the first dielectric feature so that the first dielectric feature has a reduced thickness on both first and the second sides, and forming a gate electrode layer to surround each of the first semiconductor layers of the first and second fin structures.

Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.

Abstract: A computer device, a setting method for a memory module, and a mainboard are provided. The computer device includes a memory module, a processor, and the mainboard. A basic input output system (BIOS) of the mainboard stores a custom extreme memory profile (XMP). When the processor executes the BIOS, so that the computer device displays a user interface (UI), the BIOS displays multiple default XMPs stored in the memory module and the custom XMP through the UI. The BIOS stores one of the default XMPs and the custom XMP to the memory module according to a selecting result of the one of the default XMPs and the custom XMP displayed on the UI.

Abstract: Data stream based event sequence anomaly detection for mobility customer fraud analysis is presented herein. A system obtains a sequence of events comprising respective modalities of communication that correspond to a subscriber identity associated with a communication service—the sequence of events having occurred within a defined period. Based on defined classifiers representing respective fraudulent sequences of events, the system determines, via a group of machine learning models corresponding to respective machine learning processes, whether the sequence of events satisfies a defined condition with respect to likelihood of representing a fraudulent sequence of events of the respective fraudulent sequences of events. In response to the sequence of events being determined to satisfy the defined condition, the system sends, via a user interface of the system, a notification indicating that the sequence of events has been determined to represent the fraudulent sequence of events.

Abstract: A semiconductor device includes a first active region, a second active region and a dielectric wall. The second active region disposed adjacent to the first active region, and there is a first space between the first active region and the second active region. The dielectric wall is formed within the first space and has a first sidewall and a second sidewall opposite to the first sidewall. The first sidewall and the second sidewall opposite to the first sidewall continuously extend along a plane.

Abstract: The disclosure provides an in-memory computing (IMC) memory device and an IMC method thereof. The IMC memory device includes; a memory array including a plurality of computing units, each of the computing units including a plurality of parallel-coupling computing cells, the parallel-coupling computing cells of the same computing unit receiving a same input voltage; wherein a plurality of input data is converted into a plurality input voltages; after receiving the input voltages, the computing units generate a plurality of output currents; and based on the output currents, a multiply accumulate (MAC) of the input data and a plurality of conductance of the computing cells is generated.

Abstract: An RF testing method is applied between a testing instrument and multiple devices under test at least including a first DUT and a second DUT. The testing instrument includes a signal generator and a signal analyzer. A sync signal is sent to the testing instrument and the first DUT, so that the first DUT occupies the signal generator to receive a testing signal from the signal generator. The first DUT sends an uplink signal to the signal analyzer based on the testing signal to occupy the signal analyzer for signal analysis at a first point in time. The sync signal is sent to the testing instrument and the second DUT, so that the second DUT occupies the signal generator to receive the testing signal from the signal generator at a second point in time. The first point in time is parallel to the second point in time.

Abstract: The embodiments of the disclosure provide a method for dynamically controlling shooting parameters of a camera and a tracking device. The method includes: determining a plurality of time frames, wherein the time frames include a plurality of first time frames and a plurality of second time frames; controlling the camera of the tracking device to shoot a first image with a first exposure parameter in each of the first time frames and accordingly performing an environment detection; controlling the camera of the tracking device to shoot a second image with a second exposure parameter in each of the second time frames and accordingly performing a first specific detection, wherein the second exposure parameter is lower than the first exposure parameter.

Abstract: A method for forming integrated circuit (IC) packages includes mounting dies on a strip of interconnects and applying wire bonds in regions of the strip of interconnects proximate to mold shields. The method also includes adjusting the mold shields of the strip of interconnects. The method includes flowing a mold compound on the strip of interconnects to form a strip of IC packages. Mold injection pressure causes the mold compound to flow from a first end of the strip of interconnects across the strip of interconnects to a second end of the strip of interconnects, and the mold shields impede the flow of the mold compound through the regions of the strip of interconnects proximate to the mold shields. The method includes singulating the strip of IC packages to form the IC packages.

Abstract: An X-ray device, including a sensor panel and a flexible scintillator structure disposed on the sensor panel, is provided. A manufacturing method of the X-ray device is also provided.

Abstract: Systems and methods for natural language generation by an edge computing device are disclosed. In one embodiments, a method comprises: receiving, by an edge computing device, event data from an edge event; determining, by the edge computing device, that a network connection to a cloud server is not available; extracting, by the edge computing device, features of the event data; predicting, by a local neural network of the edge computing device, an action for the edge computing device to take based on the features of the event data, wherein the action is associated with a confidence level; and determining, by the edge computing device, whether the confidence level meets a predetermined threshold value.