Abstract: An additive compound for dyeing an aluminum or aluminum alloy substrate after anodic oxidation to provide better uniformity in dyeing and hence a better finished appearance includes a main agent, an auxiliary agent, a pH stabilizer, and an antibacterial agent. The antibacterial agent includes at least one of sorbic acid, fluconazole, itraconazole, Artemisia argyi, benzyl alcohol, benzoic acid, salicylic acid, and boric acid. An additive solution and a dyeing method are also provided, the use of the compound also allows for a more rapid dyeing process.

Abstract: A circuit in a physical unit (PHY) is disclosed, the circuit comprising two trios and a combo wire therebetween, wherein each of said trios includes three wires, and wherein said combo wire is configurable as a signal, floating, or any dc voltage, furthermore, a Quad-IO block is designed for transmit data in two D-PHY lanes with the combo wire configured as a signal wire or a C-PHY trio with the combo wire configured as a shielding wire, such that the same Quad-IO block can be instantiated multiple times in a physical unit for meeting different bandwidth requirements as well as for placing pads along a same direction for preventing performance difference between D-PHY lanes or C-PHY trios.

Abstract: A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive a second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.

Abstract: A circuit in a physical unit (PHY) is disclosed, the circuit comprising two trios and a combo wire therebetween, wherein each of said trios includes three wires, and wherein said combo wire is configurable as a signal, floating, or any dc voltage, furthermore, a Quad-IO block is designed for transmit data in two D-PHY lanes with the combo wire configured as a signal wire or a C-PHY trio with the combo wire configured as a shielding wire, such that the same Quad-IO block can be instantiated multiple times in a physical unit for meeting different bandwidth requirements as well as for placing pads along a same direction for preventing performance difference between D-PHY lanes or C-PHY trios.

Abstract: Disclosed is an escalator sterilization device attached close to a handrail of an escalator and formed by a base and a sterilization module. The sterilization module has a cover in an arc shape, so that the cover can be attached closed to a surface of a handrail of the escalator, and the inner wall of the cover has plural electrode coils electrically coupled to a power supply device in the base. After the power supply device is conducted by an electric power, a high voltage power is generated to excite the electrode coils to form plasma, and the plasma is used to destroy polymorphic bacteria and microorganisms, so that the sterilization module can eliminate the bacteria on the surface of the handrail of the escalator and provide a deodorant effect.

Abstract: A regulator applied to regulate a first reference voltage on an output terminal, the regulator includes: a sensing circuit, arranged to sense a variation of the first reference voltage on the output terminal to generate a sensing signal; and a gain stage, arranged to provide an adjusting current to the output terminal in response to the sensing signal for reducing the variation of the first reference voltage, and the gain stage is coupled in parallel to a loading circuit powered by the first reference voltage.

Abstract: A clock and data recovery circuit includes a sampler, a skew compensation block, a pulse generator, and an injection locked oscillator. The injection locked oscillator generates a recovered clock signal, the pulse generator generates a pulse signal according to input data for controlling the injection locked oscillator, the skew compensation block compensates the input data and generate compensated data, and the sampler samples the compensated data according to the recovered clock signal.

Abstract: A clock and data recovery circuit includes a sampler, a skew compensation block, a pulse generator, and an injection locked oscillator. The injection locked oscillator generates a recovered clock signal, the pulse generator generates a pulse signal according to input data for controlling the injection locked oscillator, the skew compensation block compensates the input data and generate compensated data, and the sampler samples the compensated data according to the recovered clock signal.

Abstract: A clock and data recovery circuit includes a sampler, a skew compensation block, a pulse generator, and an injection locked oscillator. The injection locked oscillator generates a recovered clock signal, the pulse generator generates a pulse signal according to input data for controlling the injection locked oscillator, the skew compensation block compensates the input data and generate compensated data, and the sampler samples the compensated data according to the recovered clock signal.

Abstract: A clock and data recovery circuit includes a sampler, a skew compensation block, a pulse generator, and an injection locked oscillator. The injection locked oscillator generates a recovered clock signal, the pulse generator generates a pulse signal according to input data for controlling the injection locked oscillator, the skew compensation block compensates the input data and generate compensated data, and the sampler samples the compensated data according to the recovered clock signal.

Abstract: A regulator applied to regulate a first reference voltage on an output terminal, the regulator includes: a sensing circuit, arranged to sense a variation of the first reference voltage on the output terminal to generate a sensing signal; and a gain stage, arranged to provide an adjusting current to the output terminal in response to the sensing signal for reducing the variation of the first reference voltage, and the gain stage is coupled in parallel to a loading circuit powered by the first reference voltage.

Abstract: A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.

Abstract: A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.

Abstract: A memory controller is provided. The memory controller is powered by first and second power source and includes an input/output pin, a driver circuit, a terminal resistor, and an input buffer. The driver circuit is coupled to the input/output pin and capable of providing to a writing signal to the input/output pin. The terminal resistor is coupled between the input/output pin and the first power source. The input buffer is coupled to the input/output pin and capable of receiving a reading signal from the input/output pin. No terminal resistor is coupled between the input/output pin and the second power source.

Abstract: A method for manufacturing an insert-molded cover for electronic devices, including manufacturing a metallic body, processing the metallic body by a chemical method and forming an oxide film on a surface of the metallic body, and molding a plastic antenna lid on the metallic body by insert molding so that the plastic antenna lid is attached on the oxide film.

Abstract: A signal transmission system includes a first clock signal generator and a second clock signal generator. The first clock signal generator is configured for generating a first clock signal according to clock information derived from a transmitted signal, wherein the transmitted signal is changed in response to a frequency change of a second clock signal, and the first clock signal generator enters a frequency-unlocked state if the second clock signal has a frequency transition from a first frequency to a second frequency during a first time period. The second clock signal generator is configured for generating the second clock signal having the frequency transition from the first frequency to the second frequency during a second time period longer than the first time period such that the first clock signal generator stays in a frequency-locked state during the second time period.

Abstract: A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.

Abstract: A memory controller is provided. The memory controller is powered by first and second power source and includes an input/output pin, a driver circuit, a terminal resistor, and an input buffer. The driver circuit is coupled to the input/output pin and capable of providing to a writing signal to the input/output pin. The terminal resistor is coupled between the input/output pin and the first power source. The input buffer is coupled to the input/output pin and capable of receiving a reading signal from the input/output pin. No terminal resistor is coupled between the input/output pin and the second power source.

Abstract: Semiconductor circuit capable of mitigating unwanted effects caused by variations in a received input signal are provided, in which a main circuit receives an input signal and comprises a first current source coupled between a first node and a first power voltage to generate a first current according to a first bias voltage. A replica circuit is coupled to the main circuit to duplicate a variation in a voltage at the first node caused by a variation in the input signal and dynamically adjusts the first bias voltage according to the duplicated variation such that the first current is maintained at a constant.

Abstract: Semiconductor circuit capable of mitigating unwanted effects caused by variations in a received input signal are provided, in which a main circuit receives an input signal and comprises a first current source coupled between a first node and a first power voltage to generate a first current according to a first bias voltage. A replica circuit is coupled to the main circuit to duplicate a variation in a voltage at the first node caused by a variation in the input signal and dynamically adjusts the first bias voltage according to the duplicated variation such that the first current is maintained at a constant.