Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Abstract: Various back end of line (BEOL) layer formation techniques described herein enable reduced contact resistance, reduced surface roughness, and/or increased semiconductor device performance for BEOL layers such as interconnects and/or metallization layers.

Abstract: A semiconductor device includes a source/drain component of a transistor. A source/drain contact is disposed over the source/drain component. A source/drain via is disposed over the source/drain contact. The source/drain via contains copper. A first liner at least partially surrounds the source/drain via. A second liner at least partially surrounds the first liner. The first liner and the second liner are disposed between the source/drain contact and the source/drain via. The first liner and the second liner have different material compositions.

Abstract: A semiconductor device structure and methods of forming the same are described. In some embodiments, the structure includes an N-type source/drain epitaxial feature disposed over a substrate, a P-type source/drain epitaxial feature disposed over the substrate, a first silicide layer disposed directly on the N-type source/drain epitaxial feature, and a second silicide layer disposed directly on the P-type source/drain epitaxial feature. The first and second silicide layers include a first metal, and the second silicide layer is substantially thicker than the first silicide layer. The structure further includes a third silicide layer disposed directly on the first silicide layer and a fourth silicide layer disposed directly on the second silicide layer. The third and fourth silicide layer include a second metal different from the first metal, and the third silicide layer is substantially thicker than the fourth silicide layer.

Abstract: A semiconductor device includes a first transistor, a second transistor, a first metal silicide layer, a second metal silicide layer, and an isolation structure. The first transistor includes a first channel layer, a first gate structure, and first source/drain epitaxy structures. The second transistor includes a second channel layer, a second gate structure, and second source/drain epitaxy structures. The first metal silicide layer is over one of the first source/drain epitaxy structures. The second metal silicide layer is over one of the second source/drain epitaxy structures. The isolation structure covers the one of the first source/drain epitaxy structures and the one of the second source/drain epitaxy structures, wherein in a cross-sectional view, the one of the first source/drain epitaxy structures is separated from the isolation structure through the first metal silicide layer, while the one of the second source/drain epitaxy structures is in contact with the isolation structure.

Abstract: A method includes forming a dielectric layer over a conductive feature, and etching the dielectric layer to form an opening. The conductive feature is exposed through the opening. The method further includes forming a tungsten liner in the opening, wherein the tungsten liner contacts sidewalls of the dielectric layer, depositing a tungsten layer to fill the opening, and planarizing the tungsten layer. Portions of the tungsten layer and the tungsten liner in the opening form a contact plug.

Abstract: In one example, an electronic device may include a display screen defining a plurality of display regions. Further, the electronic device may include a camera to capture an image of an operator of the electronic device. Furthermore, the electronic device may include a controller operatively coupled to the camera and the display screen. The controller may detect an orientation of the operator's face with respect to the display screen using the captured image. Further, the controller may determine a first display region of the plurality of display regions corresponding to the detected orientation of the operators face. Furthermore, the controller may activate the first display region to position a cursor of a pointing device within the first display region.

Abstract: Semiconductor structures and methods of forming the same are provided. A method of the present disclosure includes receiving a workpiece that includes a bottom source/drain feature over a substrate, a first dielectric layer over the bottom source/drain feature, a top source/drain feature over the first dielectric layer, and a second dielectric layer over the top source/drain feature, forming a frontside opening through the second dielectric layer to expose a portion of the top source/drain feature, selectively depositing a first silicide layer on the exposed portion of the top source/drain feature, forming a top metal fill layer over the first silicide layer to fill the frontside opening, forming a backside opening through the substrate to expose a portion of the bottom source/drain feature, selectively depositing a second silicide layer on the exposed portion of the bottom source/drain feature, and forming a bottom metal fill layer on the second silicide layer.

Abstract: Provided is a manufacturing method of circuit board, including a first substrate, a second substrate, a third substrate, a fourth substrate, multiple conductive structures, and a conductive via structure. The third substrate has an opening and includes a first dielectric layer. The opening penetrates the third substrate, and the first dielectric layer fills the opening. Multiple conductive structures are formed so that the first substrate, the second substrate, the third substrate, and the fourth substrate are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, the first dielectric layer of the third substrate, and the fourth substrate. The conductive via structure is electrically connected to the first substrate and the fourth substrate to define a signal path, and the ground path surrounds the signal path.

Abstract: A light-emitting diode circuit and a light-emitting diode driving circuit are disclosed. The light-emitting diode driving circuit includes the DC-DC converter and the switch circuit. The DC-DC converter converts a DC voltage to the driving voltage for driving the light-emitting diode. One end of the switch circuit is electrically connected to the DC-DC converters and a cathode of the light-emitting diode, the other end of the circuit switching is electrically connected to a ground terminal. The switch circuit controls the connection between the DC-DC converters, the Light-emitting diodes and the ground terminal based on the control signal.

Abstract: The reworkable bonding pad layout includes a first point, a second point, a reworkable bonding pad, a first leading wire, and a second leading wire. There is a debug position defined between the first point and the second point. The reworkable bonding pad is formed at the debug position. The first leading wire may connect the reworkable bonding pad and the first point. The second leading wire may connect the reworkable bonding pad and the second point. The reworkable bonding pad is cut into a first debug area connecting with the first leading wire, and a second debug area connecting with the second leading wire.

Abstract: A clock generator includes a printed circuit board, a resonant circuit and a pair of compensating capacitors. The resonant circuit is disposed on the printed circuit board. The compensating capacitors are embedded in the printed circuit board and electrically connected to both terminals of the resonant circuit respectively.

Abstract: An organic electroluminescent device having solar cells and a fabricating method therefor are disclosed. The device comprises a transparent substrate; an organic electroluminescent device on the transparent substrate; and at least one solar cells on the transparent substrate. Besides, the device further comprises a driving unit coupled to the organic electroluminescent device; a transform unit coupled to the solar cells; and a control unit coupled to the driving unit and the transform unit.

Abstract: An organic electroluminescent device having solar cells and a fabricating method therefor are disclosed. The device comprises a transparent substrate; an organic electroluminescent device on the transparent substrate; and at least one solar cells on the transparent substrate. Besides, the device further comprises a driving unit coupled to the organic electroluminescent device; a transform unit coupled to the solar cells; and a control unit coupled to the driving unit and the transform unit.

Abstract: An organic electroluminescent device and a method therefor are disclosed. The device comprises a transparent substrate and a plurality of pixels on the transparent substrate, wherein the pixels comprise red light pixels, green light pixels and blue light pixels. In addition, the device further comprises a red light detector adjacent to the red light pixels on the transparent substrate; a green light photo-detector adjacent to the green pixels on the transparent substrate and; and a blue light photo-detector adjacent to the blue pixels on the transparent substrate.

Abstract: An organic electroluminescent device having solar cells and a fabricating method therefor are disclosed. The device comprises a transparent substrate; an organic electroluminescent device on the transparent substrate; and at least one solar cells on the transparent substrate. Besides, the device further comprises a driving unit coupled to the organic electroluminescent device; a transform unit coupled to the solar cells; and a control unit coupled to the driving unit and the transform unit.