Patents by Inventor Chih-Chien Wang

Chih-Chien Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804162
    Abstract: A method that includes forming first semiconductor layers and second semiconductor layers disposed over a substrate, wherein the first and second semiconductor layers have different material compositions, are alternatingly disposed, and extend over first and second regions of the substrate; patterning the first and the second semiconductor layers to form a first fin in the first region and a second fin in the second region; removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin; forming third semiconductor layers on the second suspended nanostructures in the second fin; and performing an anneal process to drive materials contained in the third semiconductor layers into corresponding second suspended nanostructures in the second fin.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Wang, Jui-Chien Huang, Chun-Hsiung Lin, Kuo-Cheng Chiang, Chih-Chao Chou, Pei-Hsun Wang
  • Patent number: 10795166
    Abstract: A head up display system for a vehicle is provided, including an eye tracking device and a head up display device. The eye tracking device is configured to pre-locate an initial gaze position of a driver of the vehicle before the vehicle starts moving and to detect a gaze position of the driver in real time. The head up display device includes a projector and a processor. The processor is coupled to the eye tracking device and the projector. The processor compares the gaze position with the initial gaze position, and controls the projector to project a display image to a first projection position or a second projection position according to a comparison result, wherein the first projection position corresponds to the initial gaze position and the second projection position corresponds to the gaze position. A control method of a head up display system is also provided.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: October 6, 2020
    Assignee: PEGATRON CORPORATION
    Inventors: Kuang-Ping Huang, Pei-Chin Wang, Chih-Chien Lu, Chia-Ming Lee
  • Publication number: 20200273964
    Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin structure on a substrate, in which the fin structure includes a fin stack of alternating first and second semiconductor layers and forming recesses in the fin stack at source and drain regions. The method also includes etching the second semiconductor layers to form recessed second semiconductor layers, and forming third semiconductor layers on sidewalls of the recessed second semiconductor layers. The method further includes epitaxially growing source and drain structures in the recesses, removing the recessed second semiconductor layers to form spaces between the first semiconductor layers, and oxidizing the third semiconductor layers to form inner spacers. In addition, the method includes forming a gate structure to fill the spaces and to surround the first semiconductor layers.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung LIN, Pei-Hsun WANG, Chih-Hao WANG, Kuo-Cheng CHING, Jui-Chien HUANG
  • Patent number: 10734436
    Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
  • Publication number: 20200184642
    Abstract: The present invention discloses a method for detecting skin conditions, and the method includes the steps of: capturing a skin image from a suspected subject; decomposing the skin image into an RBX image through RBX color-space transformation; and determining skin condition of the subject according to a parameter of a color model of the RBX image.
    Type: Application
    Filed: December 10, 2019
    Publication date: June 11, 2020
    Inventors: Chih-Yu Wang, Po-Han HUANG, Shu-Chen CHANG, Chia-Chen LU, Wen-Chien TSAI, Yun-Hsuan OU YANG
  • Patent number: 10651183
    Abstract: A manufacturing method of a semiconductor device includes: providing a substrate having memory and high voltage regions; sequentially forming a floating gate layer and a hard mask layer on the substrate; patterning the hard mask layer to form a first opening exposing a portion of the floating gate layer in the range of the memory region; patterning the hard mask layer and the floating gate layer to form a second opening overlapped with the high voltage region; performing a first thermal growth process to simultaneously form a first oxide structure on the portion of the floating gate layer exposed by the first opening, and to form a second oxide structure on a portion of the substrate overlapped with the second opening; removing the hard mask layer; and patterning the floating gate layer by using the first oxide structure as a mask.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 12, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Jianjun Yang, Cheng-Hua Yang, Fan-Chi Meng, Chih-Chien Chang, Shen-De Wang
  • Publication number: 20200144133
    Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.
    Type: Application
    Filed: January 8, 2020
    Publication date: May 7, 2020
    Inventors: Chih-Hao Wang, Jui-Chien Huang, Chun-Hsiung Lin, Kuo-Cheng Chiang, Chih-Chao Chou, Pei-Hsun Wang
  • Publication number: 20200135584
    Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.
    Type: Application
    Filed: October 28, 2018
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Ching, Chun-Hsiung Lin, Pei-Hsun Wang
  • Publication number: 20200135932
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate; an isolation structure at least partially surrounding the fin; an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, wherein an extended portion of the epitaxial S/D feature extends over the isolation structure; and a silicide layer disposed on the epitaxial S/D feature, the silicide layer continuously surrounding the extended portion of the epitaxial S/D feature over the isolation structure.
    Type: Application
    Filed: September 25, 2019
    Publication date: April 30, 2020
    Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
  • Publication number: 20200126798
    Abstract: A method includes forming a first dielectric layer over a semiconductor fin protruding from a substrate, forming a second dielectric layer over the first dielectric layer, then removing a portion of the semiconductor fin to form a first recess defined by portions of the first dielectric layer, followed by removing that portions of the first dielectric layer that define the first recess. Thereafter, the method proceeds to forming an epitaxial source/drain (S/D) feature in the first recess, removing the second dielectric layer to form a second recess that is disposed between the epitaxial S/D feature and remaining portions of the first dielectric layer, and subsequently forming a silicide layer over the epitaxial S/D feature, such that the silicide layer wraps around the epitaxial S/D feature.
    Type: Application
    Filed: June 18, 2019
    Publication date: April 23, 2020
    Inventors: Chun-Hsiung Lin, Shih-Cheng Chen, Chih-Hao Wang, Jung-Hung Chang, Jui-Chien Huang
  • Publication number: 20200105617
    Abstract: A method that includes forming first semiconductor layers and second semiconductor layers disposed over a substrate, wherein the first and second semiconductor layers have different material compositions, are alternatingly disposed, and extend over first and second regions of the substrate; patterning the first and the second semiconductor layers to form a first fin in the first region and a second fin in the second region; removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin; forming third semiconductor layers on the second suspended nanostructures in the second fin; and performing an anneal process to drive materials contained in the third semiconductor layers into corresponding second suspended nanostructures in the second fin.
    Type: Application
    Filed: March 27, 2019
    Publication date: April 2, 2020
    Inventors: Chih-Hao Wang, Jui-Chien Huang, Chun-Hsiung Lin, Kuo-Cheng Chiang, Chih-Chao Chou, Pei-Hsun Wang
  • Publication number: 20200102645
    Abstract: A semiconductor device is manufactured by modifying an electromagnetic field within a deposition chamber. In embodiments in which the deposition process is a sputtering process, the electromagnetic field may be modified by adjusting a distance between a first coil and a mounting platform. In other embodiments, the electromagnetic field may be adjusted by applying or removing power from additional coils that are also present.
    Type: Application
    Filed: July 12, 2019
    Publication date: April 2, 2020
    Inventors: Jen-Chun Wang, Ya-Lien Lee, Chih-Chien Chi, Hung-Wen Su
  • Patent number: 10546889
    Abstract: Implementations of the disclosure provide a method of fabricating an image sensor device. The method includes forming first trenches in a first photoresist layer using a first photomask having a first pattern to expose a first surface of a substrate, directing ions into the exposed first substrate through the first trenches to form first isolation regions in the substrate, removing the first photoresist layer, forming second trenches in a second photoresist layer using a second photomask having a second pattern to expose a second surface of the substrate, the second pattern being shifted diagonally from the first pattern by half mask pitch, directing ions into the exposed second surface through the second trenches to form second isolation regions in the substrate, the first and second isolation regions being alternatingly disposed in the substrate, and the first and second isolation regions defining pixel regions therebetween, and removing the second photoresist layer.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: January 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
  • Publication number: 20190329222
    Abstract: A method for regeneration of a carbon dioxide absorbent includes steps of a) bringing a used carbon dioxide absorbent in contact with a carbon-containing dielectric material to form a dielectric energy-susceptible combination, and b) subjecting the dielectric energy-susceptible combination to a dielectric heating to remove carbon dioxide from the used carbon dioxide absorbent for the regeneration.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 31, 2019
    Inventors: Chih-Yung CHEN, Chen-Chien WANG, Jian-Sheng SHEN
  • Publication number: 20190278094
    Abstract: A head up display system for a vehicle is provided, including an eye tracking device and a head up display device. The eye tracking device is configured to pre-locate an initial gaze position of a driver of the vehicle before the vehicle starts moving and to detect a gaze position of the driver in real time. The head up display device includes a projector and a processor. The processor is coupled to the eye tracking device and the projector. The processor compares the gaze position with the initial gaze position, and controls the projector to project a display image to a first projection position or a second projection position according to a comparison result, wherein the first projection position corresponds to the initial gaze position and the second projection position corresponds to the gaze position. A control method of a head up display system is also provided.
    Type: Application
    Filed: March 4, 2019
    Publication date: September 12, 2019
    Applicant: PEGATRON CORPORATION
    Inventors: Kuang-Ping Huang, Pei-Chin Wang, Chih-Chien Lu, Chia-Ming Lee
  • Patent number: 10335735
    Abstract: A method of capturing carbon dioxide from a source thereof includes contacting a carbon dioxide-containing source with a reactive solution that includes an absorption agent so that carbon dioxide in the carbon dioxide-containing source is absorbed by the absorption agent. The absorption agent may be potassium phosphate, potassium ethylenediamine-tetraacetate (potassium EDTA), a potassium monocarboxylate having a total of 12 or less carbon atoms, or combinations thereof.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: July 2, 2019
    Assignee: National Cheng Kung University
    Inventors: Chih-Yung Chen, Chen-Chien Wang, Jian-Sheng Shen
  • Patent number: 10333505
    Abstract: A circuit in a physical unit (PHY) is disclosed, the circuit comprising two trios and a combo wire therebetween, wherein each of said trios includes three wires, and wherein said combo wire is configurable as a signal, floating, or any dc voltage, furthermore, a Quad-IO block is designed for transmit data in two D-PHY lanes with the combo wire configured as a signal wire or a C-PHY trio with the combo wire configured as a shielding wire, such that the same Quad-IO block can be instantiated multiple times in a physical unit for meeting different bandwidth requirements as well as for placing pads along a same direction for preventing performance difference between D-PHY lanes or C-PHY trios.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: June 25, 2019
    Assignee: M31 Technology Corporation
    Inventors: Huai-Te Wang, Chih Chien Hung
  • Patent number: 10332884
    Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: June 25, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, Che-Jung Hsu, Yu-Cheng Tung, Jianjun Yang, Yuan-Hsiang Chang, Chih-Chien Chang, Weichang Liu, Shen-De Wang, Kok Wun Tan
  • Patent number: 10301334
    Abstract: A method for preparing a stabilizer containing phosphate ester, including following steps: (1) distributing a compound containing phosphorous and oxide in polar aprotic solvent to obtain a mixture; (2) adding bis(2-hydroxyethyl) terephthalate (BHET) into the mixture to carry out a reaction so as to obtain a solution; and (3) hydrolyzing the solution to obtain a stabilizer containing phosphate ester, where the stabilizer includes compounds represented by the following formulas (I) and (II): where X1, X2 and X3 are independently selected from the moiety represented by following formula (III), and R1 and R2 are independently selected from one of the linear or branched alkylene radicals comprising 2 to 4 carbon atoms The method yields a phosphate ester containing a phosphate monoester and a phosphate diester of a high content and only a minor amount of phosphoric acid in the absence of phosphate triester without the step of extraction.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: May 28, 2019
    Assignee: Far Eastern New Century Corporation
    Inventors: Hsin-Hui Cheng, Cheng-Ting Wang, Der-Ren Hwang, Chih-Chien Lin
  • Publication number: 20190088694
    Abstract: Implementations of the disclosure provide a method of fabricating an image sensor device. The method includes forming first trenches in a first photoresist layer using a first photomask having a first pattern to expose a first surface of a substrate, directing ions into the exposed first substrate through the first trenches to form first isolation regions in the substrate, removing the first photoresist layer, forming second trenches in a second photoresist layer using a second photomask having a second pattern to expose a second surface of the substrate, the second pattern being shifted diagonally from the first pattern by half mask pitch, directing ions into the exposed second surface through the second trenches to form second isolation regions in the substrate, the first and second isolation regions being alternatingly disposed in the substrate, and the first and second isolation regions defining pixel regions therebetween, and removing the second photoresist layer.
    Type: Application
    Filed: November 5, 2018
    Publication date: March 21, 2019
    Inventors: Wei-Chao CHIU, Chih-Chien WANG, Feng-Jia SHIU, Ching-Sen KUO, Chun-Wei CHANG, Kai TZENG