Patents by Inventor Chih-Ching Chien
Chih-Ching Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240144966Abstract: The present disclosure generally relates to a dual free layer two dimensional magnetic recording read head. The read head comprises a first lower shield, a first sensor disposed over the first lower shield, a first upper shield disposed over the first sensor, a read separation gap (RSG) disposed on the first upper shield, a second lower shield disposed over the RSG, a second sensor disposed over the second lower shield, and a second upper shield disposed over the second sensor. In some embodiments, the second lower shield comprises a CoFeHf layer. In another embodiment, the second lower shield is a synthetic antiferromagnetic multilayer comprising a first shield layer, a second shield layer, and a CoFe/Ru/CoFe anti-ferromagnetic coupling layer or a Ru layer disposed therebetween, the first and second shield layers comprising NiFe and CoFe. In yet another embodiment, the second lower shield comprises layers of Ru, IrMn, and NiFe.Type: ApplicationFiled: July 26, 2023Publication date: May 2, 2024Applicant: Western Digital Technologies, Inc.Inventors: Ming MAO, Chen-Jung CHIEN, Goncalo Marcos BAIÃO DE ALBUQUERQUE, Chih-Ching HU, Yung-Hung WANG, Ming JIANG
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Publication number: 20240071413Abstract: The present disclosure generally relates to a dual free layer (DFL) read head and methods of forming thereof. In one embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a stripe height of the DFL sensor, depositing a rear bias (RB) adjacent to the DFL sensor, defining a track width of the DFL sensor and the RB, and depositing synthetic antiferromagnetic (SAF) soft bias (SB) side shields adjacent to the DFL sensor. In another embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a track width of the DFL sensor, depositing SAF SB side shields adjacent to the DFL sensor, defining a stripe height of the DFL sensor and the SAF SB side shield, depositing a RB adjacent to the DFL sensor and the SAF SB side shield, and defining a track width of the RB.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: Western Digital Technologies, Inc.Inventors: Ming MAO, Yung-Hung WANG, Chih-Ching HU, Chen-Jung CHIEN, Carlos CORONA, Hongping YUAN, Ming JIANG, Goncalo Marcos BAIÃO DE ALBUQUERQUE
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Patent number: 10909047Abstract: The present invention discloses a solid state drive (SSD) control device including: a multi-interface compatible physical layer circuit operable to generate a physical layer output signal according to a serializer/deserializer (SerDes) reception signal; and a processing circuit operable to make the solid state drive control device adapt to one of several interface types in accordance with the physical layer output signal.Type: GrantFiled: April 12, 2019Date of Patent: February 2, 2021Assignee: RAYMX MICROELECTRONICS CORP.Inventors: Cheng-Yu Chen, Chih-Ching Chien
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Patent number: 10866850Abstract: A memory device includes a memory module and a control module. The control module is coupled to the memory module and is configured to store data into the memory module according to a first mapping table. The control module includes a storing unit and a guaranteeing unit. The storing unit is configured to store the first mapping table. The guaranteeing unit is coupled to the storing unit and is configured to determine whether the first mapping table is correct or not. The guaranteeing unit is further configured to issue an error signal in a state where the first mapping table is incorrect.Type: GrantFiled: March 12, 2019Date of Patent: December 15, 2020Assignee: RAYMX MICROELECTRONICS CORP.Inventors: Yen-Chung Chen, Cheng-Yu Chen, Chih-Ching Chien
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Patent number: 10817437Abstract: The present invention discloses a solid state drive (SSD) control device including: a multi-interface compatible physical layer circuit operable to generate a physical layer output signal according to a serializer/deserializer (SerDes) reception signal; an input/output (I/O) circuit operable to generate at least one terminal output signal according to signal variation of at least one terminal; and a processing circuit operable to make the solid state drive control device adapt to one of several interface types in accordance with the physical layer output signal and/or the at least one terminal output signal.Type: GrantFiled: January 9, 2019Date of Patent: October 27, 2020Assignee: RAYMX MICROELECTRONICS CORP.Inventors: Cheng-Yu Chen, Chih-Ching Chien
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Patent number: 10802961Abstract: An apparatus and a method for accessing a plurality of memory blocks is disclosed. The An apparatus comprises: a memory circuit configured to store a recording table, wherein the recording table corresponds to quality index of the plurality of memory blocks; and a control circuit configured to group the plurality of memory blocks to a first memory group and a second memory group according to the quality index; to enable to access the memory blocks in the first memory group, and to disable to access the memory blocks in the second memory group.Type: GrantFiled: March 27, 2019Date of Patent: October 13, 2020Assignee: RAYMX MICROELECTRONICS CORP.Inventors: Yen-Chung Chen, Chih-Ching Chien, Li-Chun Huang, Han-Ting Tsai, Wei-Ren Hsu
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Patent number: 10776288Abstract: The present invention discloses a memory control device and method compatible to multiple types of interface the memory control device comprises: a multi-interface physical layer circuit configured to couple to a host, to receive a differential signal from the host, to detect at least one of characteristics of the differential signal to generate a physical layer output signal and to generate a physical layer output signal according to a detected result, wherein a frequency of the differential signal is higher than hundreds of KHz; and a processing circuit, coupled between the multi-interface physical layer circuit and a memory module, configured to receive the physical layer output signal from the multi-interface physical layer circuit, to determine the differential signal complies with one of a specification of an first type of interface and that of a second type of interface according to the physical layer output signal, and to adapt an operation mode of the memory control device to one of the multiple typeType: GrantFiled: August 12, 2019Date of Patent: September 15, 2020Assignee: RAYMX MICROELECTRONICS CORP.Inventors: Cheng-Yu Chen, Chih-Ching Chien
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Patent number: 10776011Abstract: A computing system including a memory, a processor and a solid state disk is provided. The memory stores a disk access driver program. The solid state disk includes a storage circuit and a control circuit. The control circuit includes a processing unit, a first access path and a second access path. The processing unit communicates with the processor through the first access path. The processor executes the driver program that enables the processor to process a disk access command for directly accessing the storage circuit of the solid state disk through the second access path.Type: GrantFiled: March 6, 2019Date of Patent: September 15, 2020Assignee: RAYMX MICROELECTRONICS CORP.Inventors: Cheng-Yu Chen, Chih-Ching Chien, Yen-Chung Chen
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Publication number: 20190361819Abstract: The present invention discloses a memory control device and method compatible to multiple types of interface the memory control device comprises: a multi-interface physical layer circuit configured to couple to a host, to receive a differential signal from the host, to detect at least one of characteristics of the differential signal to generate a physical layer output signal and to generate a physical layer output signal according to a detected result, wherein a frequency of the differential signal is higher than hundreds of KHz; and a processing circuit, coupled between the multi-interface physical layer circuit and a memory module, configured to receive the physical layer output signal from the multi-interface physical layer circuit, to determine the differential signal complies with one of a specification of an first type of interface and that of a second type of interface according to the physical layer output signal, and to adapt an operation mode of the memory control device to one of the multiple typeType: ApplicationFiled: August 12, 2019Publication date: November 28, 2019Inventors: CHENG-YU CHEN, CHIH-CHING CHIEN
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Publication number: 20190303286Abstract: An apparatus and a method for accessing a plurality of memory blocks is disclosed. The An apparatus comprises: a memory circuit configured to store a recording table, wherein the recording table corresponds to quality index of the plurality of memory blocks; and a control circuit configured to group the plurality of memory blocks to a first memory group and a second memory group according to the quality index; to enable to access the memory blocks in the first memory group, and to disable to access the memory blocks in the second memory group.Type: ApplicationFiled: March 27, 2019Publication date: October 3, 2019Inventors: Yen-Chung Chen, Chih-Ching Chien, Li-Chun Huang, Han-Ting Tsai, Wei-Ren Hsu
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Publication number: 20190236036Abstract: The present invention discloses a solid state drive (SSD) control device including: a multi-interface compatible physical layer circuit operable to generate a physical layer output signal according to a serializer/deserializer (SerDes) reception signal; and a processing circuit operable to make the solid state drive control device adapt to one of several interface types in accordance with the physical layer output signal.Type: ApplicationFiled: April 12, 2019Publication date: August 1, 2019Inventors: CHENG-YU CHEN, CHIH-CHING CHIEN
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Publication number: 20190213066Abstract: A memory device includes a memory module and a control module. The control module is coupled to the memory module and is configured to store data into the memory module according to a first mapping table. The control module includes a storing unit and a guaranteeing unit. The storing unit is configured to store the first mapping table. The guaranteeing unit is coupled to the storing unit and is configured to determine whether the first mapping table is correct or not. The guaranteeing unit is further configured to issue an error signal in a state where the first mapping table is incorrect.Type: ApplicationFiled: March 12, 2019Publication date: July 11, 2019Inventors: Yen-Chung CHEN, Cheng-Yu CHEN, Chih-Ching CHIEN
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Publication number: 20190196714Abstract: A computing system including a memory, a processor and a solid state disk is provided. The memory stores a disk access driver program. The solid state disk includes a storage circuit and a control circuit. The control circuit includes a processing unit, a first access path and a second access path. The processing unit communicates with the processor through the first access path. The processor executes the driver program that enables the processor to process a disk access command for directly accessing the storage circuit of the solid state disk through the second access path.Type: ApplicationFiled: March 6, 2019Publication date: June 27, 2019Inventors: Chen-Yu CHEN, Chih-Ching CHIEN, Yen-Chung CHEN
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Publication number: 20190146933Abstract: The present invention discloses a solid state drive (SSD) control device including: a multi-interface compatible physical layer circuit operable to generate a physical layer output signal according to a serializer/deserializer (SerDes) reception signal; an input/output (I/O) circuit operable to generate at least one terminal output signal according to signal variation of at least one terminal; and a processing circuit operable to make the solid state drive control device adapt to one of several interface types in accordance with the physical layer output signal and/or the at least one terminal output signal.Type: ApplicationFiled: January 9, 2019Publication date: May 16, 2019Inventors: CHENG-YU CHEN, CHIH-CHING CHIEN
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Patent number: 10255123Abstract: A memory device includes a memory module and a control module. The control module is coupled to the memory module and is configured to store data into the memory module according to a first mapping table. The control module includes a storing unit and a guaranteeing unit. The storing unit is configured to store the first mapping table. The guaranteeing unit is coupled to the storing unit and is configured to determine whether the first mapping table is correct or not. The guaranteeing unit is further configured to issue an error signal in a state where the first mapping table is incorrect.Type: GrantFiled: October 21, 2016Date of Patent: April 9, 2019Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Yen-Chung Chen, Cheng-Yu Chen, Chih-Ching Chien
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Patent number: 10248559Abstract: The present disclosure provides a weighting-type data relocation control device for controlling data relocation of a non-volatile memory which includes used blocks and unused blocks. Each used block is associated with a first parameter and a second parameter. The control device executes the following steps: multiplying the first and second parameters by a first and a second weightings respectively to obtain a priority index, in which at least one of the parameters and/or at least one of the weightings relate(s) to a thermal detection result; comparing the priority index with at least a threshold to obtain a comparison result; and if the comparison result corresponding to a used storage block of the used blocks reaches a predetermined threshold, transferring valid data of the used storage block to one of the unused blocks.Type: GrantFiled: October 19, 2016Date of Patent: April 2, 2019Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Yen-Chung Chen, Chih-Ching Chien, Fu-Hsin Chen
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Patent number: 10235050Abstract: A computing system including a memory, a processor and a solid state disk is provided. The memory stores a disk access driver program. The solid state disk includes a storage circuit and a control circuit. The control circuit includes a processing unit, a first access path and a second access path. The processing unit communicates with the processor through the first access path. The processor executes the driver program that enables the processor to process a disk access command for directly accessing the storage circuit of the solid state disk through the second access path.Type: GrantFiled: May 17, 2017Date of Patent: March 19, 2019Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Cheng-Yu Chen, Chih-Ching Chien, Yen-Chung Chen
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Patent number: 10198368Abstract: The present invention discloses a solid state drive (SSD) control device including: a multi-interface compatible physical layer circuit operable to generate a physical layer output signal according to a serializer/deserializer (SerDes) reception signal; an input/output (I/O) circuit operable to generate at least one terminal output signal according to signal variation of at least one terminal; and a processing circuit operable to make the solid state drive control device adapt to one of several interface types in accordance with the physical layer output signal and/or the at least one terminal output signal.Type: GrantFiled: May 23, 2017Date of Patent: February 5, 2019Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Cheng-Yu Chen, Chih-Ching Chien
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Publication number: 20170351624Abstract: The present invention discloses a solid state drive (SSD) control device including: a multi-interface compatible physical layer circuit operable to generate a physical layer output signal according to a serializer/deserializer (SerDes) reception signal; an input/output (I/O) circuit operable to generate at least one terminal output signal according to signal variation of at least one terminal; and a processing circuit operable to make the solid state drive control device adapt to one of several interface types in accordance with the physical layer output signal and/or the at least one terminal output signal.Type: ApplicationFiled: May 23, 2017Publication date: December 7, 2017Inventors: CHENG-YU CHEN, CHIH-CHING CHIEN
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Publication number: 20170336975Abstract: A computing system including a memory, a processor and a solid state disk is provided. The memory stores a disk access driver program. The solid state disk includes a storage circuit and a control circuit. The control circuit includes a processing unit, a first access path and a second access path. The processing unit communicates with the processor through the first access path. The processor executes the driver program that enables the processor to process a disk access command for directly accessing the storage circuit of the solid state disk through the second access path.Type: ApplicationFiled: May 17, 2017Publication date: November 23, 2017Inventors: Cheng-Yu CHEN, Chih-Ching CHIEN, Yen-Chung CHEN