Patents by Inventor Chih-Ching Shih
Chih-Ching Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136293Abstract: Provided are a package structure having a joint structure and a method of forming the same. The package structure includes: a first under bump metallurgy (UBM) structure disposed on a first dielectric layer, wherein the first UBM structure at least comprises: a barrier layer embedded in the first dielectric layer; and an upper metal layer disposed over the barrier layer, wherein a sidewall of the barrier layer is laterally offset outward from a sidewall of the upper metal layer, and a portion of a top surface of the barrier layer is exposed by the first dielectric layer; and a solder layer disposed on the first UBM structure and contacting the upper metal layer.Type: ApplicationFiled: January 31, 2023Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Wu, Wen-Chih Chiou, Ying-Ching Shih
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Patent number: 11967546Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.Type: GrantFiled: July 21, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
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Publication number: 20240128211Abstract: Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.Type: ApplicationFiled: April 27, 2023Publication date: April 18, 2024Inventors: Chih-Wei WU, An-Jhih SU, Hua-Wei TSENG, Ying-Ching SHIH, Wen-Chih CHIOU, Chun-Wei CHEN, Ming Shih YEH, Wei-Cheng WU, Der-Chyang YEH
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Patent number: 11955459Abstract: A package structure is provided. The package structure includes a first die and a second die, a dielectric layer, a bridge, an encapsulant, and a redistribution layer structure. The dielectric layer is disposed on the first die and the second die. The bridge is electrically connected to the first die and the second die, wherein the dielectric layer is spaced apart from the bridge. The encapsulant is disposed on the dielectric layer and laterally encapsulating the bridge. The redistribution layer structure is disposed over the encapsulant and the bridge. A top surface of the bridge is in contact with the RDL structure.Type: GrantFiled: March 7, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Hang Liao, Chih-Wei Wu, Jing-Cheng Lin, Szu-Wei Lu, Ying-Ching Shih
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Publication number: 20240107780Abstract: A system on chip (SoC) die package is attached to a redistribution structure of a semiconductor device package such that a top surface of the SoC die package is above a top surface of an adjacent memory die package. This may be achieved through the use of various attachment structures that increase the height of the SoC die package. After encapsulating the memory die package and the SoC die package in an encapsulation layer, the encapsulation layer is grinded down. The top surface of the SoC die package being above the top surface of the adjacent memory die package results in the top surface of the SoC die package being exposed through the encapsulation layer after the grinding operation. This enables heat to be dissipated through the top surface of the SoC die package.Type: ApplicationFiled: January 5, 2023Publication date: March 28, 2024Inventors: Chih-Wei WU, Ying-Ching SHIH, Wen-Chih CHIOU, An-Jhih SU, Chia-Nan YUAN
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Publication number: 20240105701Abstract: A package structure and methods for forming the package structure are provided. The package structure includes a package component, an encapsulant disposed around the package component, and a redistribution structure disposed over the package component and the encapsulant. The package component includes a substrate, a protection structure, which includes an organic material, over a first surface of the substrate, and a multi-layered structure encapsulated by the protection structure. Sidewalls of the multi-layered structure are spaced apart from the encapsulant by the protection structure.Type: ApplicationFiled: January 11, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Wu, Ying-Ching Shih, Wen-Chih Chiou
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Publication number: 20240096732Abstract: Some implementations described herein provide techniques and apparatuses for a fixture including a semiconductor die package and methods of formation. The semiconductor die package is mounted to an interposer. In addition to the semiconductor die package, the fixture includes a lid component having a top structure and footing structures that connect the lid component to the interposer. The fixture includes a thermal interface material between a top surface of the semiconductor die package and the top structure of the lid component. The footing structures, connected to the interposer using deposits of an epoxy material, provide increase a structural rigidity of the fixture relative to another fixture not including the footing structures.Type: ApplicationFiled: January 13, 2023Publication date: March 21, 2024Inventors: Chih-Hao CHEN, Li-Hui CHENG, Ying-Ching SHIH
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Publication number: 20240071847Abstract: A semiconductor package including two different adhesives and a method of forming are provided. The semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. The first adhesive may encircle the package component and the heat transfer layer. The lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. A material of the second adhesive may be different from a material of the first adhesive.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Inventors: Yi-Huan Liao, Ping-Yin Hsieh, Chih-Hao Chen, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
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Publication number: 20240071857Abstract: A semiconductor device includes a package substrate, a package component and at least one adhesive pattern. The package component has a thermal interface material (TIM) layer thereon. The adhesive pattern has a first surface facing the package substrate and a second surface opposite to the first surface, and the second surface of the at least one adhesive pattern is substantially coplanar with a surface of the TIM layer.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
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Publication number: 20240071855Abstract: A package structure including a semiconductor die, a redistribution circuit structure, a backside dielectric layer, conductive terminals, an electronic device, and an underfill is provided. The semiconductor die laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes redistribution conductive layers and thermal enhancement structures electrically insulated from the redistribution conductive layers, and the thermal enhancement structures are thermally coupled to the semiconductor die. The backside dielectric layer is disposed on the redistribution circuit structure. The conductive terminals penetrate through the backside dielectric layer. The electronic device is disposed over the backside dielectric layer and electrically connected to the redistribution circuit structure through the conductive terminals.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Wu, Ying-Ching Shih, Wen-Chih Chiou
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Patent number: 7981753Abstract: A device for providing electrostatic discharge (ESD) protection is provided. The device includes a semiconductor substrate having a drain, a source, and a gate formed therein. The drain contains a region having a resistance that is higher than the resistance of the remainder of the drain and the source. The gate region is in contact with this higher resistance region and the source. In one embodiment, the higher resistance is lacking silicide in order to provide the higher resistance. A method of forming a device for providing ESD protection is included.Type: GrantFiled: January 6, 2010Date of Patent: July 19, 2011Assignee: Altera CorporationInventors: Hugh Sungki O, Chih-Ching Shih, Cheng-Hsiung Huang, Yow-Juang Bill Liu
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Patent number: 7955923Abstract: A trigger circuit is provided for a pull-down device by connecting a diode between the I/O pad and the body of the pull-down device. In one embodiment, the pull-down device is formed as a plurality of discrete transistors in a single well. The drain of each transistor is connected through a ballast resistor to the I/O pad; and the source of each transistor is connected through a ballast resistor to ground. The trigger circuit is a diode formed in a different well from that of the transistors. The cathode of the diode is connected to the I/O pad and the anode is connected to the transistor well through a center tap located between the transistors. Preferably, the transistors are NMOS transistors formed in a P-well. Advantageously, the diode is an N+/PLDD diode. Alternatively, the diode is an N+/P diode where the P region is formed by an ESD implant. In other embodiments the diode is formed in the same well as the transistors.Type: GrantFiled: July 28, 2010Date of Patent: June 7, 2011Assignee: Altera CorporationInventors: Antonio Gallerano, Cheng-Hsiung Huang, Chih-Ching Shih, Jeffrey T. Watt
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Patent number: 7821050Abstract: A transistor fabricated on a semiconductor substrate includes a source and a drain in the substrate; a gate on the substrate, the gate being insulated from the substrate by gate dielectric; barrier layers covering two sides of the gate and the gate dielectric; spacers of high-k material covering the barrier layers; and nitride spacers covering the spacers of high-k material. The spacers of high-k material significantly increase the node capacitance of the transistor and therefore reduce the transistor's soft error rate.Type: GrantFiled: July 31, 2006Date of Patent: October 26, 2010Assignee: Altera CorporationInventors: Yowjuang (Bill) Liu, Cheng-Hsiung Huang, Chih-Ching Shih
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Patent number: 7808047Abstract: A trigger circuit is provided for a pull-down device by connecting a diode between the I/O pad and the body of the pull-down device. In one embodiment, the pull-down device is formed as a plurality of discrete transistors in a single well. The drain of each transistor is connected through a ballast resistor to the I/O pad; and the source of each transistor is connected through a ballast resistor to ground. The trigger circuit is a diode formed in a different well from that of the transistors. The cathode of the diode is connected to the I/O pad and the anode is connected to the transistor well through a center tap located between the transistors. Preferably, the transistors are NMOS transistors formed in a P-well. Advantageously, the diode is an N+/PLDD diode. Alternatively, the diode is an N+/P diode where the P region is formed by an ESD implant. In other embodiments the diode is formed in the same well as the transistors.Type: GrantFiled: August 31, 2007Date of Patent: October 5, 2010Assignee: Altera CorporationInventors: Antonio Gallerano, Cheng-Hsiung Huang, Chih-Ching Shih, Jeffrey T. Watt
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Patent number: 7772591Abstract: Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) transistor serves as an electrically-programmable antifuse. The antifuse transistor has source, drain, gate, and substrate terminals. The gate has an associated gate oxide. In its unprogrammed state, the gate oxide is intact and the antifuse has a relatively high resistance. During programming, the gate oxide breaks down, so in its programmed state the antifuse transistor has a relatively low resistance. The antifuse transistor can be programmed by injecting hot carriers into the substrate of the device in the vicinity of the drain. Because there are more hot carriers at the drain than at the substrate, the gate oxide is stressed asymmetrically, which enhances programming efficiency. Feedback can be used to assist in turning the antifuse transistor on to inject the hot carriers.Type: GrantFiled: November 10, 2006Date of Patent: August 10, 2010Assignee: Altera CorporationInventors: Chih-Ching Shih, Cheng H. Huang, Hugh Sung-Ki O, Yow-Juang (Bill) Liu
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Patent number: 7671416Abstract: A device for providing electrostatic discharge (ESD) protection is provided. The device includes a semiconductor substrate having a drain, a source, and a gate formed therein. The drain contains a region having a resistance that is higher than the resistance of the remainder of the drain and the source. The gate region is in contact with this higher resistance region and the source. In one embodiment, the higher resistance is lacking silicide in order to provide the higher resistance. A method of forming a device for providing ESD protection is included.Type: GrantFiled: September 30, 2004Date of Patent: March 2, 2010Assignee: Altera CorporationInventors: Hugh Sungki O, Chih-Ching Shih, Cheng-Hsiung Huang, Yow-Juang Bill Liu
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Patent number: 7638847Abstract: An ESD protection structure includes, in part, a NMOS transistor having a source and drain in a well in a substrate and a gate on the substrate with the source and drain being connected between ground and a series diode, and the gate being connected to ground. The structure further includes a diode having a cathode connected to the input pad and an anode connected to the well so that the diode is reverse-biased in the event of a positive voltage ESD event on the input pad. As a result, in a positive voltage ESD event, the avalanche effect rapidly injects current into the substrate and therefore into the base of the parasitic bipolar transistor so as to trigger the transistor into conduction and discharge the ESD pulse. Alternatively, the diode is a Zener diode and the current is generated by the Zener effect. A complementary structure provides protection against a negative ESD pulse.Type: GrantFiled: January 25, 2006Date of Patent: December 29, 2009Assignee: Altera CorporationInventors: Hugh Sungki O, Chih-Ching Shih, Cheng-Hsiung Huang, Yow-Juang Bill Liu
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Publication number: 20090164811Abstract: Embodiments include methods, apparatus, and systems for analyzing data in an infrastructure. One embodiment includes a method that senses environmental data at equipment racks in an infrastructure, identifies patterns in the environmental data, and uses the patterns to modify the infrastructure to improve thermal management in the infrastructure.Type: ApplicationFiled: October 31, 2008Publication date: June 25, 2009Inventors: Ratnesh Sharma, Chih Ching Shih, Chandrakant Patel, John Sontag
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Patent number: 7511533Abstract: Circuits, methods, and apparatus for output devices having parasitic transistors for a higher output current drive. One such MOS output device includes a parasitic bipolar transistor that assists output voltage transitions. The parasitic transistor may be inherent in the structure of the MOS device. Alternately, one or more regions, such as implanted or diffused regions, may be added to the MOS device to form or enhance the parasitic bipolar device. The parasitic transistor is turned on when during an appropriate output transition and turned off once the transition is complete. The parasitic device may be turned on by injecting current into the bulk of a pull-down device, by pulling current out of the bulk of a pull-up device, or by tying the bulk of the output device to an appropriate voltage, such as VCC for a pull-down device or ground for a pull-up device.Type: GrantFiled: February 27, 2006Date of Patent: March 31, 2009Assignee: Altera CorporationInventors: Hugh Sungki O, Chih-Ching Shih, Cheng-Hsiung Huang, Yow-Juang Bill Liu
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Patent number: 7471493Abstract: A pair of SCR devices connected in antiparallel between first and second nodes. Each SCR device comprises an NPN and a PNP bipolar transistor. Reverse-biased Zener diodes are used for triggering the NPN bipolar transistor in each SCR device when it breaks down in an ESD event. Advantageously, additional Zener diodes are provided for pre-charging the PNP transistor of each SCR device at the same time, thereby reducing the delay time for turning on the PNP bipolar transistor. In addition, the breakdown current of the Zener diodes is preferably maximized by reducing the P-well and N-well resistance of the SCRs. This is achieved by connecting external resistances between the base of each bipolar transistor and the node to which the emitter of the transistor is connected.Type: GrantFiled: February 28, 2006Date of Patent: December 30, 2008Assignee: Altera CorporationInventors: Cheng-Hsiung Huang, Chih-Ching Shih, Hugh Sung-Ki O, Yowjuang (Bill) Liu