Patents by Inventor Chih-Chiu Wang

Chih-Chiu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11937515
    Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Hsiang-Ku Shen, Liang-Wei Wang, Chen-Chiu Huang, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 9509366
    Abstract: The present application provides an interference estimation circuit which includes a signal generator, a first symbol extractor and a first mixer. The signal generator generates an orthogonal signal orthogonal to partial symbols of a plurality of pilot signals. The first symbol extractor extracts partial symbols of a first decoded signal decoded from a received signal wherein the first decoded signal contains one of the plurality of pilot signals, and includes an input node for receiving the first decoded signal and an output node for outputting a first extracted signal. The first extracted signal is substantially orthogonal to the orthogonal signal. The first mixer is coupled to the signal generator for receiving the orthogonal signal and to the first symbol extractor for receiving the first extracted signal, and outputs a first mixed signal of the orthogonal signal and the first extracted signal for interference estimation.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: November 29, 2016
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Chi-Yuan Peng, Chih-Chiu Wang
  • Patent number: 7778364
    Abstract: A signal strength estimation circuit for a code division multiple access system comprises a channel compensator, a demodulator, an extractor and an average circuit. The channel compensator compensates different channel effect upon a received signal and outputs first and second compensated signals wherein the received signal comprises a first signal and a second signal. The demodulator electrically connected to the channel compensator demodulates the first and second compensated signals and outputs first and second demodulated signals wherein the demodulator demodulates the first and second compensated signals by corresponding 4 bits pilot patterns when each of the first and second compensated signals only has 2 pilot bits in a slot and the second signal is obtained by space time transmit diversity encoding the first signal. The extractor coupled to the demodulator respectively extracts first and second pilot signals from the first and second demodulated signals.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: August 17, 2010
    Assignee: Via Technologies, Inc.
    Inventors: Chih-Chiu Wang, Huoy-Bing Lim
  • Publication number: 20090028228
    Abstract: A signal strength estimation circuit for a code division multiple access system comprises a channel compensator, a demodulator, an extractor and an average circuit. The channel compensator compensates different channel effect upon a received signal and outputs first and second compensated signals wherein the received signal comprises a first signal and a second signal. The demodulator electrically connected to the channel compensator demodulates the first and second compensated signals and outputs first and second demodulated signals wherein the demodulator demodulates the first and second compensated signals by corresponding 4 bits pilot patterns when each of the first and second compensated signals only has 2 pilot bits in a slot and the second signal is obtained by space time transmit diversity encoding the first signal. The extractor coupled to the demodulator respectively extracts first and second pilot signals from the first and second demodulated signals.
    Type: Application
    Filed: July 26, 2007
    Publication date: January 29, 2009
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Chih-Chiu Wang, Huoy-Bing Lim
  • Publication number: 20080247472
    Abstract: The present application provides an interference estimation circuit which includes a signal generator, a first symbol extractor and a first mixer. The signal generator generates an orthogonal signal orthogonal to partial symbols of a plurality of pilot signals. The first symbol extractor extracts partial symbols of a first decoded signal decoded from a received signal wherein the first decoded signal contains one of the plurality of pilot signals, and includes an input node for receiving the first decoded signal and an output node for outputting a first extracted signal. The first extracted signal is substantially orthogonal to the orthogonal signal. The first mixer is coupled to the signal generator for receiving the orthogonal signal and to the first symbol extractor for receiving the first extracted signal, and outputs a first mixed signal of the orthogonal signal and the first extracted signal for interference estimation.
    Type: Application
    Filed: April 4, 2007
    Publication date: October 9, 2008
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Chi-Yuan Peng, Chih-Chiu Wang