Patents by Inventor Chih-Chuan Chen

Chih-Chuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978773
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a base structure. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure sandwiching the channel structures. The semiconductor device structure further includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. In addition, the semiconductor device structure includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Shih-Chuan Chiu, Cheng-Chi Chuang, Chih-Hao Wang
  • Patent number: 11972537
    Abstract: A method for flattening a three-dimensional shoe upper template is provided. The method includes providing a three-dimensional last model, obtaining a three-dimensional grid model, obtaining a three-dimensional thickened grid model, obtaining a two-dimensional initial-value grid model, and obtaining a two-dimensional grid model with the smallest energy value. A system and a non-transitory computer-readable medium for performing the method are also provided. The method makes it possible to precisely flatten a three-dimensional last model with a non-developable surface and thereby convert the three-dimensional last model into a two-dimensional grid model.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: April 30, 2024
    Assignee: YU JUNG CHANG TECHNOLOGY CO., LTD.
    Inventors: Chih-Chuan Chen, Wei-Hsiang Tsai, Chin-Yu Chen, Ching-Cherng Sun, Jann-Long Chern, Yu-Kai Lin
  • Patent number: 11973294
    Abstract: The present invention includes a plug bolt and a bolt seat. The plug bolt includes a bolt pin having an upper buckle and a receiving hole that receives a circuit device including an RFID chip and a lower contact point therein. The bolt seat includes a lower monopole antenna, a locking hole into which the bolt pin is insertable, and a lower buckle by which the upper buckle is positionable. The bolt pin is manipulatable to lock up with the bolt seat and set the lower monopole antenna and the lower contact point in electrical connection to activate the RFID chip. The lower monopole antenna includes a spring at a location corresponding to the locking hole. The spring provides preloading for keeping electrical connection between the lower monopole antenna and the lower contact point. The spring is set to match with a frequency band of a host device.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: April 30, 2024
    Inventor: Chih-Chuan Chen
  • Patent number: 11955515
    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Yu-Ming Lin
  • Patent number: 11949016
    Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hao Lin, Chih-Chuan Yang, Chih-Hsuan Chen, Bwo-Ning Chen, Cha-Hon Chou, Hsin-Wen Su, Chih-Hsiang Huang
  • Publication number: 20240101527
    Abstract: A compound of Formula (I) below, or a pharmaceutically acceptable salt, stereoisomer, solvate, or prodrug thereof: in which R1, R2, R3, R5, R6, and R7 are defined as in the SUMMARY section. Further disclosed are a method of using the above-described compound, salt, stereoisomer, solvate, or prodrug for treating microbial infections and a pharmaceutical composition containing the same.
    Type: Application
    Filed: October 23, 2020
    Publication date: March 28, 2024
    Applicant: TAIGEN BIOTECHNOLOGY CO., LTD.
    Inventors: Chu-Chung Lin, Hung-Chuan Chen, Chiayn Chiang, Chih-Ming Chen
  • Publication number: 20240097301
    Abstract: The present invention discloses an integrated choke assembly comprising: a base having a main body structure, a first protruding part and a second protruding part. A first choke has a first magnetic core and a first winding, wherein the first protruding part is arranged through the first opening of the first magnetic core so that the first choke is arranged on the upper surface of the main body structure, and the first winding is wound on the first magnetic core. A second choke has a second magnetic core and a second winding, wherein the second protruding part is arranged through the second opening of the second magnetic core so that the second choke is arranged on the lower surface of the main body structure, and the second winding is wound on the second magnetic core.
    Type: Application
    Filed: October 16, 2022
    Publication date: March 21, 2024
    Inventors: Pang-Chuan CHEN, Chih-Shin HUANG, Shu-Cheng LEE
  • Patent number: 11935947
    Abstract: An enhancement mode high electron mobility transistor (HEMT) includes a group III-V semiconductor body, a group III-V barrier layer and a gate structure. The group III-V barrier layer is disposed on the group III-V semiconductor body, and the gate structure is a stacked structure disposed on the group III-V barrier layer. The gate structure includes a gate dielectric and a group III-V gate layer disposed on the gate dielectric, and the thickness of the gate dielectric is between 15 nm to 25 nm.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: March 19, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Shin-Chuan Huang, Wen-Jung Liao, Chun-Liang Hou
  • Publication number: 20240022016
    Abstract: The present invention includes a plug bolt and a bolt seat. The plug bolt includes a bolt pin having a receiving hole that receives a circuit device including an RFID chip electrically connected with a main circuit and a radiation unit. The receiving hole defines a hole body arranged in an axial direction, and an open hole bottom at a bottom of the hole body. The main circuit includes a lower contact point. The radiation unit induces an effect of coupling feed with respect to the hold body to make the bolt pin forming an upper monopole antenna. The bolt seat includes a lower monopole antenna and a locking hole into which the bolt pin is insertable. When the lower monopole antenna is electrically connected with the lower contact point, the upper and lower monopole antennas jointly form a standard dipole antenna to emit a signal that is monitorable.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 18, 2024
    Inventor: CHIH-CHUAN CHEN
  • Publication number: 20240022023
    Abstract: The present invention includes a plug bolt and a bolt seat. The plug bolt includes a bolt pin having an upper buckle and a receiving hole that receives a circuit device including an RFID chip and a lower contact point therein. The bolt seat includes a lower monopole antenna, a locking hole into which the bolt pin is insertable, and a lower buckle by which the upper buckle is positionable. The bolt pin is manipulatable to lock up with the bolt seat and set the lower monopole antenna and the lower contact point in electrical connection to activate the RFID chip. The lower monopole antenna includes a spring at a location corresponding to the locking hole. The spring provides preloading for keeping electrical connection between the lower monopole antenna and the lower contact point. The spring is set to match with a frequency band of a host device.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 18, 2024
    Inventor: CHIH-CHUAN CHEN
  • Publication number: 20230057550
    Abstract: A method for flattening a three-dimensional shoe upper template is provided. The method includes providing a three-dimensional last model, obtaining a three-dimensional grid model, obtaining a three-dimensional thickened grid model, obtaining a two-dimensional initial-value grid model, and obtaining a two-dimensional grid model with the smallest energy value. A system and a non-transitory computer-readable medium for performing the method are also provided. The method makes it possible to precisely flatten a three-dimensional last model with a non-developable surface and thereby convert the three-dimensional last model into a two-dimensional grid model.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 23, 2023
    Inventors: Chih-Chuan CHEN, Wei-Hsiang TSAI, Chin-Yu CHEN, Ching-Cherng SUN, Jann-Long CHERN, Yu-Kai LIN
  • Patent number: 11525282
    Abstract: An insertion pin includes a pin member on which a circuit board, an inspection antenna, and an inspection chip are mounted. The circuit board includes a main circuit, a main chip, and an inspection circuit set in an open-circuit condition with respect to the inspection antenna and the inspection chip. A lock base includes a main antenna matching the main chip. When the lock base and the pin member are combined and locked together, the main chip is electrically connected with the main antenna to emit a first signal for monitoring with an identification device, and the inspection circuit is electrically connectable with the inspection chip and the inspection antenna to emit a second signal to allow a mobile phone to carry out quality control to determine if the first signal is in normal operation. Cutting off the insertion pin terminates both the first and second signals.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: December 13, 2022
    Inventor: Chih-Chuan Chen
  • Publication number: 20210056868
    Abstract: The present invention comprises a plug-bolt set with a circuit board and a detection antenna on a bolt-piece and a lock-seat set with a main antenna. The circuit board is set with a chip, a main circuit, and a secondary circuit. When the lock-seat and the bolt-piece are engaged and locked; the chip, the main circuit, and the main antenna are electrically connected to emit a first signal for providing the identification host to monitor, and controlling the secondary circuit to be electrically connected with the chip and the detection antenna to emit a second signal. The second signal can be used for the mobile phone software to do the quality control of the first signal. The first and second signals can be cut-off simultaneously when the plug-bolt is broken. This allows the end customer to do the actual test and quality control using the mobile phone.
    Type: Application
    Filed: August 25, 2019
    Publication date: February 25, 2021
    Inventor: Chih-Chuan Chen
  • Patent number: 10916161
    Abstract: The present invention comprises a plug-bolt set with a circuit board and a detection antenna on a bolt-piece and a lock-seat set with a main antenna. The circuit board is set with a chip, a main circuit, and a secondary circuit. When the lock-seat and the bolt-piece are engaged and locked; the chip, the main circuit, and the main antenna are electrically connected to emit a first signal for providing the identification host to monitor, and controlling the secondary circuit to be electrically connected with the chip and the detection antenna to emit a second signal. The second signal can be used for the mobile phone software to do the quality control of the first signal. The first and second signals can be cut-off simultaneously when the plug-bolt is broken. This allows the end customer to do the actual test and quality control using the mobile phone.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: February 9, 2021
    Inventor: Chih-Chuan Chen
  • Publication number: 20200386009
    Abstract: An insertion pin includes a pin member on which a circuit board, an inspection antenna, and an inspection chip are mounted. The circuit board includes a main circuit, a main chip, and an inspection circuit set in an open-circuit condition with respect to the inspection antenna and the inspection chip. A lock base includes a main antenna matching the main chip. When the lock base and the pin member are combined and locked together, the main chip is electrically connected with the main antenna to emit a first signal for monitoring with an identification device, and the inspection circuit is electrically connectable with the inspection chip and the inspection antenna to emit a second signal to allow a mobile phone to carry out quality control to determine if the first signal is in normal operation. Cutting off the insertion pin terminates both the first and second signals.
    Type: Application
    Filed: June 4, 2019
    Publication date: December 10, 2020
    Inventor: CHIH-CHUAN CHEN
  • Patent number: 10580275
    Abstract: A bolt includes a conductor having an accommodation hole and a circuit board installed in the accommodation hole, where the upper part of the conductor is covered with an insulating sleeve, and the lower part thereof is configured with a first engagement portion, a RFID chip and lower contact of the circuit board is formed into a control circuit, and the lower contact is allowed to be protruded out of the bottom end of the accommodation hole. An antenna and elastic sheet are configured inside the bolt seat, and the outer peripheral thereof is configured with an insertion hole and second engagement portion adapted to position the first engagement portion, the elastic sheet have a pre-pressure to allow the antenna, control circuit and conductor to be in electric connection with one another. Whereby, the electric connection can be interrupted when the bolt is cut.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: March 3, 2020
    Inventor: Chih-Chuan Chen
  • Patent number: 10510272
    Abstract: The present invention consists of a plug bolt and a bolt seat. The plug bolt comprises a conductor and a circuit board; the conductor has a first stuck-buckle, an accommodation-hole, and a top-cover; the circuit board is set with an RFID chip, an upper contact point, and a lower contact point. The RFID chip forms a first far-field antenna loop through the first pin, the upper contact point, the top-cover, and the conductor. The bolt seat is equipped with an elastic device, an internal antenna, an inserting-hole, and a second stuck-buckle, thereby controlling the elastic device to provide a pre-pressure to the internal antenna to electrically connect with the lower contact point. When the RFID chip is activated, the internal antenna forms a second far-field antenna loop and synchronously activate the first one; which the first and second far-field antenna loops can be cut-off when the top-cover is worn.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: December 17, 2019
    Inventor: Chih-Chuan Chen
  • Publication number: 20190287362
    Abstract: A bolt includes a conductor having an accommodation hole and a circuit board installed in the accommodation hole, where the upper part of the conductor is covered with an insulating sleeve, and the lower part thereof is configured with a first engagement portion, a RFID chip and lower contact of the circuit board is formed into a control circuit, and the lower contact is allowed to be protruded out of the bottom end of the accommodation hole. An antenna and elastic sheet are configured inside the bolt seat, and the outer peripheral thereof is configured with an insertion hole and second engagement portion adapted to position the first engagement portion, the elastic sheet have a pre-pressure to allow the antenna, control circuit and conductor to be in electric connection with one another. Whereby, the electric connection can be interrupted when the bolt is cut.
    Type: Application
    Filed: March 13, 2018
    Publication date: September 19, 2019
    Inventor: Chih-Chuan Chen
  • Publication number: 20190243190
    Abstract: A pixel array substrate includes a substrate, pixel units, and signal lines. Each pixel unit includes an active device, a first insulation layer, a common electrode, a second insulation layer, and a pixel electrode. The common electrode is disposed on the first insulation layer and has openings. The pixel electrode is disposed on the second insulation layer and overlapped with the common electrode. The pixel electrode is electrically connected to the active device. The signal lines are disposed on the substrate and electrically connected to the active device, respectively. The openings include at least one first opening, and an orthogonal projection of the at least one first opening on the substrate is located between orthogonal projections of the pixel electrodes on the substrate and orthogonal projections of the signal lines on the substrate. A display panel including the pixel array substrate is also provided.
    Type: Application
    Filed: April 18, 2018
    Publication date: August 8, 2019
    Applicant: Chunghwa Picture Tubes, LTD.
    Inventors: Chen-De Lee, Chun-Ming Huang, Chih-Chuan Chen
  • Publication number: 20190121185
    Abstract: A display mother panel including a first motherboard, a second motherboard, a plurality of sealant structures and a plurality of spacers is provided. The second motherboard is stacked over the first motherboard. The sealant structures are disposed between the first motherboard and the second motherboard. An area surrounded by each of the sealant structures includes a display region and a non-display region surrounding the display region, and a peripheral region is between two adjacent sealant structures. The spacers are disposed on a lower surface of the second motherboard which is relatively close to the first motherboard and at least located in the non-display region and the peripheral region. The display mother panel can provide preferable structure reliability and display quality. Moreover, each display panel made from the display mother panel is also provided.
    Type: Application
    Filed: December 15, 2017
    Publication date: April 25, 2019
    Applicant: Chunghwa Picture Tubes, LTD.
    Inventors: Kan-Ju Liu, Yi-Fen Su, Chih-Chuan Chen