Abstract: A method for flattening a three-dimensional shoe upper template is provided. The method includes providing a three-dimensional last model, obtaining a three-dimensional grid model, obtaining a three-dimensional thickened grid model, obtaining a two-dimensional initial-value grid model, and obtaining a two-dimensional grid model with the smallest energy value. A system and a non-transitory computer-readable medium for performing the method are also provided. The method makes it possible to precisely flatten a three-dimensional last model with a non-developable surface and thereby convert the three-dimensional last model into a two-dimensional grid model.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: Disclosed is a thermal conduction-electrical conduction isolated circuit board with a ceramic substrate and a power transistor embedded, mainly comprising: a dielectric material layer, a heat-dissipating ceramic block, a securing portion, a stepped metal electrode layer, a power transistor, and a dielectric material packaging, wherein a via hole is formed in the dielectric material layer, the heat-dissipating ceramic block is correspondingly embedded in the via hole, the heat-dissipating ceramic block has a thermal conductivity higher than that of the dielectric material layer and a thickness less than that of the dielectric material layer, the stepped metal electrode layer conducts electricity and heat for the power transistor, the dielectric material packaging is configured to partially expose the source connecting pin, drain connecting pin, and gate connecting pin of the encapsulated stepped metal electrode layer.

Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.

Abstract: An antiferroelectric field effect transistor (Anti-FeFET) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. The antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. This enables the antiferroelectric layer in the FeFET to provide a sharper/larger voltage drop for an erase operation of the FeFET (e.g., in which the FeFET switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.

Abstract: A compound of Formula (I) below, or a pharmaceutically acceptable salt, stereoisomer, solvate, or prodrug thereof: in which R1, R2, R3, R5, R6, and R7 are defined as in the SUMMARY section. Further disclosed are a method of using the above-described compound, salt, stereoisomer, solvate, or prodrug for treating microbial infections and a pharmaceutical composition containing the same.

Abstract: A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.

Abstract: A recycle apparatus includes a conveyor, a flattening device, and a cutting tool. The conveyor includes a first roller and a second roller opposite to each other. The flattening device is located aside the first roller and the second roller. The cutting tool is located aside the flattening device. The flattening device is located between the first roller and the second roller of the conveyor and the cutting tool. The first roller and the second roller is configured to press and feed the photovoltaic module to the flattening device for allowing the photovoltaic module to be flattened by the flattening device, and then the flattened photovoltaic module is fed to the cutting tool by the first roller and the second roller for allowing the back sheet to be separated from the glass sheet assembly by the cutting tool.

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

Abstract: An electronic device includes a substrate, at least one electronic element and a heat dissipating electromagnetic shielding structure. The heat dissipating electromagnetic shielding structure is disposed on the substrate and covers the at least one electronic element, wherein the heat dissipating electromagnetic shielding structure includes a shielding frame and a heatsink. The shielding frame includes a plurality of spring members. The spring members are bent toward the substrate and partially abut against the heatsink. When the heatsink and the shielding frame are correspondingly arranged, a shielding space is defined, the electronic element is disposed in the shielding space, and a heat generated by the at least one electronic element is conducted out of the shielding space via the heatsink.

Abstract: An electronic device includes a substrate, at least one electronic element and a heat dissipating electromagnetic shielding structure. The heat dissipating electromagnetic shielding structure is disposed on the substrate and covers the at least one electronic element, wherein the heat dissipating electromagnetic shielding structure includes a shielding frame and a heatsink. The shielding frame includes a plurality of spring members. The spring members are bent toward the substrate and partially abut against the heatsink. When the heatsink and the shielding frame are correspondingly arranged, a shielding space is defined, the electronic element is disposed in the shielding space, and a heat generated by the at least one electronic element is conducted out of the shielding space via the heatsink.

Abstract: An electronic device is disclosed. The electronic device includes a display unit, a light sensor, and a processor. The display unit has a brightness value. The light sensor senses an ambient light to generate a light intensity signal. The processor is coupled to the display unit and the light sensor and accesses a program instruction from a memory to perform the following steps: continuously receiving the light intensity signal from the light sensor; smoothing a plurality of light intensity signals to generate a plurality of smoothing signals; and maintaining the brightness value of the display unit for a preset time period and then determining whether to adjust the brightness value when a difference generated by subtracting a previous smoothing signal of a target smoothing signal of the smoothing signals from the target smoothing signal is less than the first threshold or greater than the second threshold.

Abstract: An electronic device is disclosed. The electronic device includes a display unit, a light sensor, and a processor. The display unit has a brightness value. The light sensor senses an ambient light to generate a light intensity signal. The processor is coupled to the display unit and the light sensor and accesses a program instruction from a memory to perform the following steps: continuously receiving the light intensity signal from the light sensor; smoothing a plurality of light intensity signals to generate a plurality of smoothing signals; and maintaining the brightness value of the display unit for a preset time period and then determining whether to adjust the brightness value when a difference generated by subtracting a previous smoothing signal of a target smoothing signal of the smoothing signals from the target smoothing signal is less than the first threshold or greater than the second threshold.

Abstract: A wireless communication device includes a base, a first antenna module, and a second antenna module. The base has a first bearing surface and a second bearing surface disposed opposite to the first bearing surface. The first antenna module is disposed on the first bearing surface. The second antenna module is disposed on the second bearing surface. Upon the structure of the wireless communication device, the dissipation efficiency and signal transmission/reception performance generated by the antenna of the wireless communication device can be improved.

Abstract: A wireless communication device includes a base, a first antenna module, and a second antenna module. The base has a first bearing surface and a second bearing surface disposed opposite to the first bearing surface. The first antenna module is disposed on the first bearing surface. The second antenna module is disposed on the second bearing surface. Upon the structure of the wireless communication device, the dissipation efficiency and signal transmission/reception performance generated by the antenna of the wireless communication device can be improved.

Abstract: A transmission device having optical fiber high definition digital audio-video data interface (HDMI/DVI/UDI), in which optical fiber is utilized as the physical connection for the logical channels of the transmission device, and is used to carry images, voices and auxiliary data of the logic channels. For the half-duplex transmission mode utilized by the display data channel, the reverse unit, the serial unit, and the multi-serial unit are properly arranged, thus fulfilling the DC balance requirement of optical fiber transmission, and resolving the lower tolerance rate shortcomings of the I2C bus specification of display data channel (DDC) and the customer electronics control (CEC) channel.

Abstract: Techniques are described to monitor charging of an integrated circuit during manufacturing processes. In one example, an integrated circuit includes first and second pads adapted to be charged by charge carriers during manufacture of the integrated circuit. The integrated circuit also includes a reference nonvolatile memory cell comprising a floating gate and a control gate, wherein the control gate is coupled to the first pad. The integrated circuit further includes a charging protection device coupled to the control gate of the reference memory cell and adapted to limit the gate voltage of the control gate induced by the charge carriers. In addition, the integrated circuit includes a charging monitor nonvolatile memory cell comprising a floating gate and a control gate, wherein the control gate is coupled to the second pad but not to a charging protection device adapted to limit the gate voltage of the control gate.

Abstract: A transmission device having optical fiber high definition digital audio-video data interface (HDMI/DVI/UDI), in which optical fiber is utilized as the physical connection for the logical channels of the transmission device, and is used to carry images, voices and auxiliary data of the logic channels. For the half-duplex transmission mode utilized by the display data channel, the reverse unit, the serial unit, and the multi-serial unit are properly arranged, thus fulfilling the DC balance requirement of optical fiber transmission, and resolving the lower tolerance rate shortcomings of the I2C bus specification of display data channel (DDC) and the customer electronics control (CEC) channel.

Abstract: A method for actively controlling he fine-tuning and impedance matching using a laser process is provided, including the use of a laser process equipment, a monitor device, and a feedback controller. The laser process equipment is for performing laser soldering or laser etching. The monitor device is for monitoring the target metrics of the target circuits. The feedback controller is for receiving the feedback from the monitor device and issuing control signals to the laser process equipment.

Abstract: An EEPROM device exhibiting high saturation current and low signal propagation delay and a process for fabricating the device that includes the formation of refractory metal silicide regions in the source and the drain regions and the gate electrode of an MOS transistor within an EEPROM memory cell. A floating-gate protect layer is formed over the floating-gate electrode and a relatively thick cap oxide layer is formed to overlie the floating-gate protect layer and the source and drain regions and gate electrode of the MOS transistor. A doped oxide layer is formed to overlie the cap oxide layer. The cap oxide layer is formed to a thickness sufficient to create strain in the channel region of the MOS transistor, while not having a thickness that could cause poor data retention in the EEPROM memory cell.