Patents by Inventor Chih-Chuan SU

Chih-Chuan SU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12361994
    Abstract: A semiconductor memory structure includes bottom electrodes formed over a substrate. The structure also includes first magnetic tunneling junction (MTJ) elements formed over the bottom electrodes in a first region and a second region of the substrate. The structure also includes second MTJ elements formed over the first MTJ elements in the first region and the second region. The structure also includes top electrodes formed over the second MTJ elements. The first MTJ elements in the first region are narrower than the second MTJ elements in the first region, and the second MTJ elements in the second region are narrower than the first MTJ elements in the second region.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: July 15, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chuan Su, Yu-Jen Wang, Liang-Wei Wang, Dian-Hau Chen
  • Publication number: 20250070064
    Abstract: An embodiment is a device including a first die and a substrate including a first surface and a second surface opposite the first surface. The device also includes an active device on the first surface of the substrate. The device also includes a first interconnect structure on the first surface of the substrate. The device also includes a through substrate via extending through the first interconnect structure and the substrate to the second surface of the substrate, the through substrate via being electrically coupled to metallization patterns in the first interconnect structure. The device also includes one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the through substrate via.
    Type: Application
    Filed: January 3, 2024
    Publication date: February 27, 2025
    Inventors: Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang, Hsin-Feng Chen, Tsung-Chieh Hsiao, Chih Chuan Su, Dian-Hau Chen
  • Publication number: 20240379361
    Abstract: A semiconductor device structure and a formation method are provided. The method includes forming an opening in a semiconductor body, and the semiconductor body is p-type doped. The method also includes introducing n-type dopants into the semiconductor body to form a modified portion near the opening, and the modified portion is p-type doped. The method further includes forming a dielectric layer along the sidewalls and the bottom of the opening. In addition, the method includes forming a conductive structure over the dielectric layer to fill the opening.
    Type: Application
    Filed: May 11, 2023
    Publication date: November 14, 2024
    Inventors: Chih-Chuan SU, Liang-Wei WANG, Tsung-Chieh HSIAO, Dian-Hau CHEN
  • Publication number: 20230292629
    Abstract: A method for forming a semiconductor memory structure includes forming an MTJ stack over a substrate. The method also includes etching the MTJ stack to form an MTJ device. The method also includes depositing a metal layer over a top surface and sidewalls of the MTJ device. The method also includes oxidizing the metal layer to form an oxidized metal layer. The method also includes depositing a cap layer over the oxidized metal layer. The method also includes oxidizing the cap layer to form an oxidized cap layer. The method also includes removing an un-oxidized portion of the cap layer.
    Type: Application
    Filed: March 9, 2022
    Publication date: September 14, 2023
    Inventors: Tzu-Ting LIU, Yu-Jen WANG, Chih-Pin CHIU, Hung-Chao KAO, Chih-Chuan SU, Liang-Wei WANG, Chen-Chiu HUANG, Dian-Hau CHEN
  • Publication number: 20230223063
    Abstract: A semiconductor memory structure includes bottom electrodes formed over a substrate. The structure also includes first magnetic tunneling junction (MTJ) elements formed over the bottom electrodes in a first region and a second region of the substrate. The structure also includes second MTJ elements formed over the first MTJ elements in the first region and the second region. The structure also includes top electrodes formed over the second MTJ elements. The first MTJ elements in the first region are narrower than the second MTJ elements in the first region, and the second MTJ elements in the second region are narrower than the first MTJ elements in the second region.
    Type: Application
    Filed: January 10, 2022
    Publication date: July 13, 2023
    Inventors: Chih-Chuan SU, Yu-Jen WANG, Liang-Wei WANG, Dian-Hau CHEN