Patents by Inventor Chih Chuang
Chih Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12189299Abstract: A digital lithography system includes adjacent scan regions, exposure units located above the scan regions, a memory, and a processing device operatively coupled to the memory. The exposure units include a first exposure unit associated with a first scan region and a second exposure unit associated with a second scan region. The processing device is to initiate a digital lithography process to pattern a substrate disposed on a stage in accordance with instructions. The processing device is to further perform a first pass of the first exposure unit over a stitching region at an interface of the first scan region and the second scan region at a first time. The processing device is to further perform a second pass of the second exposure unit over the stitching region at a second time that varies from the first time by less than forty seconds.Type: GrantFiled: February 28, 2023Date of Patent: January 7, 2025Assignee: Applied Materials, Inc.Inventors: Ying-Chiao Wang, Thomas L Laidig, Chun-Chih Chuang, Frederick Lie, Chen-Yuan Hsieh, Chun-Cheng Yeh
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Publication number: 20240406093Abstract: A method of determining routing path for a TSN system includes determining a plurality of candidate disjoint path pairs of each of a first plurality of streams according to a network topology; initializing a plurality of final routing path pairs used for the first plurality of streams and a plurality of background streams according to a first plurality of lengths of the first plurality of candidate disjoint path pairs; selecting a plurality of temporary routing path pairs used for the first plurality of streams and the plurality of background streams according to the first plurality of parameters; updating the first plurality of parameters according to the plurality of temporary routing path pairs; and replacing the plurality of temporary routing path pairs with the plurality of final routing path pairs in response to the plurality of temporary routing path pairs being better than the plurality of final routing path pairs.Type: ApplicationFiled: November 29, 2023Publication date: December 5, 2024Applicant: Moxa Inc.Inventors: Ching-Chih Chuang, Yuan-Yao Shih, Chung-Kai Hung, Ai-Chun Pang, Chung-Wei Lin
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Patent number: 12158308Abstract: A heat dissipation device is provided and includes: a first vapor chamber filled with a first working fluid therein and used for contacting at least one heat source; at least one heat transfer structure disposed on a side of the first vapor chamber; and a second vapor chamber filled with a second working fluid therein and connected to the first vapor chamber via the heat transfer structure, where the first working fluid absorbs heat of the heat source and then vaporizes, and the vaporized first working fluid transfers the heat to the second working fluid via the heat transfer structure.Type: GrantFiled: July 7, 2022Date of Patent: December 3, 2024Assignee: AURAS TECHNOLOGY CO., LTD.Inventors: Chih-Wei Chen, Tien-Yao Chang, Che-Wei Kuo, Hsiang-Chih Chuang, Jyun-Wei Huang, Kang-Ming Fan
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Publication number: 20240377721Abstract: A method includes: providing a photomask used in extreme ultra violet (EUV) lithography; determining a bias voltage of an electron beam writer system, the bias voltage applicable to an inspection operation and a repairing operation; and performing the repairing operation on the photomask by the electron beam writer system with the bias voltage.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Inventors: HAO-MING CHANG, CHING-CHIH CHUANG, HSIAO-CHEN LI
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Patent number: 12140858Abstract: A method includes: providing a photomask used in extreme ultra violet (EUV) lithography; receiving information of the photomask; determining a bias voltage of an electron beam writer system according to the information; and performing a repairing operation on the photomask by the electron beam writer system with the bias voltage.Type: GrantFiled: July 30, 2023Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hao-Ming Chang, Ching-Chih Chuang, Hsiao-Chen Li
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Patent number: 12140871Abstract: Embodiments of the present disclosure generally relate to lithography systems. More particularly, embodiments of the present disclosure relate to a method, a system, and a software application for a lithography process to control transmittance rate of write beams and write gray tone patterns in a single exposure operation. In one embodiment, a plurality of shots are provided by an image projection system in a lithography system to a photoresist layer. The plurality of shots exposes the photoresist layer to an intensity of light emitted from the image projection system. The local transmittance rate of the plurality of shots within an exposure area is varied to form varying step heights in the exposure area of the photoresist layer.Type: GrantFiled: October 21, 2022Date of Patent: November 12, 2024Assignee: Applied Materials, Inc.Inventors: YingChiao Wang, Chi-Ming Tsai, Chun-chih Chuang, Yung Peng Hu
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Publication number: 20240304705Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.Type: ApplicationFiled: May 16, 2024Publication date: September 12, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
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Publication number: 20240288778Abstract: A digital lithography system includes adjacent scan regions, exposure units located above the scan regions, a memory, and a processing device operatively coupled to the memory. The exposure units include a first exposure unit associated with a first scan region and a second exposure unit associated with a second scan region. The processing device is to initiate a digital lithography process to pattern a substrate disposed on a stage in accordance with instructions. The processing device is to further perform a first pass of the first exposure unit over a stitching region at an interface of the first scan region and the second scan region at a first time. The processing device is to further perform a second pass of the second exposure unit over the stitching region at a second time that varies from the first time by less than forty seconds.Type: ApplicationFiled: February 28, 2023Publication date: August 29, 2024Inventors: Ying-Chiao Wang, Thomas L Laidig, Chun-Chih Chuang, Frederick Lie, Chen-Yuan Hsieh, Chun-Cheng Yeh
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Publication number: 20240231239Abstract: Embodiments of the present disclosure generally relate to lithography systems. More particularly, embodiments of the present disclosure relate to a method, a system, and a software application for a lithography process to control transmittance rate of write beams and write gray tone patterns in a single exposure operation. In one embodiment, a plurality of shots are provided by an image projection system in a lithography system to a photoresist layer. The plurality of shots exposes the photoresist layer to an intensity of light emitted from the image projection system. The local transmittance rate of the plurality of shots within an exposure area is varied to form varying step heights in the exposure area of the photoresist layer.Type: ApplicationFiled: October 21, 2022Publication date: July 11, 2024Inventors: YingChiao WANG, Chi-Ming TSAI, Chun-chih CHUANG, Yung Peng HU
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Patent number: 12021134Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.Type: GrantFiled: December 1, 2022Date of Patent: June 25, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
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Publication number: 20240178102Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.Type: ApplicationFiled: April 21, 2023Publication date: May 30, 2024Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
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Publication number: 20240134287Abstract: Embodiments of the present disclosure generally relate to lithography systems. More particularly, embodiments of the present disclosure relate to a method, a system, and a software application for a lithography process to control transmittance rate of write beams and write gray tone patterns in a single exposure operation. In one embodiment, a plurality of shots are provided by an image projection system in a lithography system to a photoresist layer. The plurality of shots exposes the photoresist layer to an intensity of light emitted from the image projection system. The local transmittance rate of the plurality of shots within an exposure area is varied to form varying step heights in the exposure area of the photoresist layer.Type: ApplicationFiled: October 20, 2022Publication date: April 25, 2024Inventors: YingChiao WANG, Chi-Ming TSAI, Chun-chih CHUANG, Yung Peng HU
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Publication number: 20240136299Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Wei-Yu Chen, Chun-Chih Chuang, Kuan-Lin Ho, Yu-Min Liang, Jiun Yi Wu
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Patent number: 11894312Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.Type: GrantFiled: July 20, 2022Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Yu Chen, Chun-Chih Chuang, Kuan-Lin Ho, Yu-Min Liang, Jiun Yi Wu
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Publication number: 20240037764Abstract: Systems and techniques are described herein for processing video data. In some examples, a process is described that can include obtaining a plurality of frames, determining a scene cut in the plurality of frames, and determining a smoothed histogram based on the determined scene cut. For instance, the process can include determining a first characteristic of at least a first frame of the plurality of frames and a second characteristic of at least a second frame of the plurality of frames, determining whether a difference between the first characteristic and the second characteristic is greater than a threshold difference, and determining the scene cut based a determination that the difference between the first characteristic and the second characteristic is greater than the threshold difference.Type: ApplicationFiled: September 15, 2021Publication date: February 1, 2024Inventors: Shang-Chih CHUANG, Zhongshan WANG, Yi-Chun LU
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Publication number: 20240040715Abstract: In one or more embodiments, an information handling system may include multiple fans, a chassis configured to house components of the information handling system, and at least one mat fastened to the chassis, among others. For example, the chassis may include multiple holes through the chassis. For instance, the at least one mat may cover the multiple holes. In one or more embodiments, the at least one mat and the multiple holes may be configured to reduce acoustic energy within the chassis produced by the multiple fans.Type: ApplicationFiled: July 26, 2022Publication date: February 1, 2024Inventors: CHIH-CHIA HUANG, WAN-NIEN CHEN, HUNG-CHIH CHUANG, CHUNG-CHIEN WU
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Patent number: 11855388Abstract: A floating electrical connector includes a housing with a tubular portion. An axis is defined in a center of the tubular portion. Several floating terminals are arranged around the axis and are partially connected. Each floating terminal has an inner terminal sheet on an inner side and a spring structure on an outer side. Each spring structure is connected to one of the inner terminal sheets. A portion of the inner terminal sheet is inserted into the tubular portion and arranged along an inner peripheral surface of the tubular portion. The portion of each inner terminal sheet located in the tubular portion has an electronic contact bulging inward. Several external pins are electrically connected around the floating terminals. When a conductive pin is inserted into the tubular portion, the spring structures could elastically deform, allowing the tubular portion to adapt to a horizontal deviation or a skew deviation of the conductive pin, providing a greater tolerance for alignment deviations.Type: GrantFiled: March 14, 2022Date of Patent: December 26, 2023Assignee: ALPHA NETWORKS INC.Inventors: Chih-Kuang Wang, Ying-Chieh Shih, I-Feng Lo, Chin-Chih Chuang
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Publication number: 20230413483Abstract: A heat dissipation module includes a main vapor chamber, at least one auxiliary vapor chamber, a main heat dissipation fin set and at least one auxiliary heat dissipation fin set. The auxiliary vapor chamber is in fluid communication with the main vapor chamber, the main heat dissipation fin set is installed on the main vapor chamber, the auxiliary heat dissipation fin set is connected to the auxiliary vapor chamber, and the auxiliary vapor chamber is arranged between the main heat dissipation fin set and the auxiliary heat dissipation fin set.Type: ApplicationFiled: August 15, 2022Publication date: December 21, 2023Inventors: Chih-Wei CHEN, Cheng-Ju CHANG, Hsiang-Chih CHUANG, Jyun-Wei HUANG, Yi-Le CHENG
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Publication number: 20230367198Abstract: A method includes: providing a photomask used in extreme ultra violet (EUV) lithography; receiving information of the photomask; determining a bias voltage of an electron beam writer system according to the information; and performing a repairing operation on the photomask by the electron beam writer system with the bias voltage.Type: ApplicationFiled: July 30, 2023Publication date: November 16, 2023Inventors: HAO-MING CHANG, CHING-CHIH CHUANG, HSIAO-CHEN LI
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Publication number: 20230365063Abstract: An around view monitoring system for a vehicle includes cameras, an image processing unit and an integrated control unit. The cameras are configured to shoot peripheral images of the vehicle. The image processing unit is connected to the cameras and is configured to receive the peripheral images of the vehicle. The integrated control unit is connected to the image processing unit, and is configured to select predetermined relevant parameters of the vehicle to calibrate and splice the peripheral images so as to form around view monitoring images and to output the corresponding around view monitoring images according to the type of the vehicle. Therefore, the around view monitoring system can provide proper and corresponding around view monitoring images according to different types of vehicles.Type: ApplicationFiled: May 9, 2023Publication date: November 16, 2023Inventors: YING-CHIH CHUANG, HAN-YUN CHEN, CHIAO-YU CHEN