Abstract: A display apparatus is provided. The display apparatus includes a display module and multiple light-emitting driving circuits. Each of the light-emitting driving circuits includes a timing control circuit and a driving circuit. The timing control circuit receives multiple clock signals and a previous light-emitting timing signal to provide a light-emitting timing signal and an internal voltage. The driving circuit receives a first phase signal among multiple phase signals and the internal voltage to provide a light-emitting driving signal to the display module based on the first phase signal and the internal voltage. The phase signals all present disabled levels during a vertical blank period.

Abstract: An electronic device includes: a first substrate, wherein the first substrate is flexible; a second substrate disposed corresponding to the first substrate, wherein the second substrate is flexible; and a first conductive layer disposed on the first substrate. The first conductive layer includes: a first conductive pattern for receiving a first electrode signal and including a first bonding part; and a second conductive pattern for receiving a second electrode signal and including a second bonding part. The electronic device further includes: a second conductive layer disposed on the second substrate and electrically connected to the second conductive pattern; and a first metal layer disposed between the first substrate and at least one of the first bonding part and the second bonding part and is electrically connected to the at least one of the first bonding part and the second bonding part.

Abstract: Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.

Abstract: A cover used in a ventilation fan includes a noise reduction structure and a shelter. The noise reduction structure has an air inlet, a flat portion surrounding the air inlet, and a peripheral portion surrounding the flat portion. The sidewall of the flat portion extends in a vertical direction from the peripheral portion. The bottom surface of the flat portion extends in a horizontal direction from the sidewall, and is a flat surface. The shelter is disposed on the peripheral portion and covers the air inlet.

Abstract: An eye-diagram index analytic method includes: calculating a transfer function of multiple coupled lines; converting the transfer function into a pulse response; calculating an eye-diagram index according to the pulse response; and correcting the eye-diagram index according to peak distortion analysis.

Abstract: A system and method of performing tensor operations with a multi-step operation processing system in a memory-efficient manner. The method includes the stages of dividing an N-dimensional tensor into a set of tensor slices. The tensor slices consist of one or more consecutive rows. The tensor slices may further be segmented. The tensor slice segments, along with the dependency data, form based on the tensor dependencies are used for an tensor operation computation to generate a first result. Each processed slice segment is fused into a result slice by removing extra data used in the computation. This process is repeated for each slice to be processed and combined into a final processed tensor result.

Abstract: Embodiments of the present disclosure generally relate to lithography systems. More particularly, embodiments of the present disclosure relate to a method, a system, and a software application for a lithography process to control transmittance rate of write beams and write gray tone patterns in a single exposure operation. In one embodiment, a plurality of shots are provided by an image projection system in a lithography system to a photoresist layer. The plurality of shots exposes the photoresist layer to an intensity of light emitted from the image projection system. The local transmittance rate of the plurality of shots within an exposure area is varied to form varying step heights in the exposure area of the photoresist layer.

Abstract: Artificial intelligence is an increasingly important sector of the computer industry. However, artificial intelligence is an extremely computationally intensive field such that performing artificial intelligence calculations can be expensive, time consuming, and energy consuming. Fortunately, many of the calculations required for artificial intelligence applications can be performed in parallel such that specialized linear algebra matrix processors can greatly increase computational performance. But even with linear algebra matrix processors; performance can be limited due to complex data dependencies. Without proper coordination, linear algebra matrix processors may end up idle or spending large amounts of time moving data around. Thus, this document discloses methods for efficiently scheduling linear algebra matrix processors.

Abstract: Artificial intelligence is an increasingly important sector of the computer industry. However, artificial intelligence is extremely computationally intensive field such that it can be expensive, time consuming, and energy consuming. Fortunately, many of the calculations required for artificial intelligence can be performed in parallel such that specialized processors can great increase computational performance. Specifically, artificial intelligence generally requires large numbers of matrix operations to implement neural networks such that specialized Matrix Processor circuits can improve performance. But a neural network is more than a collection of matrix operations; it is a set of specifically coordinated matrix operations with complex data dependencies. Without proper coordination, Matrix Processor circuits may end up idle or spending large amounts of time loading in different weight matrix data.

Abstract: Disclosed are systems and methods for processing a multilayer neural network incorporating skip connections while reducing the memory footprint and processing time of processing a neural network. The method comprises loading within a memory partition with a portion of an input tensor and a portion of layer weights associated with computing a portion of the one or more intermediate layer tensors associated with a first portion of the skip connection tensor. Next, a neural processing unit is used to recompute portions of the skip connection tensor using the portion of the input tensor and associated weights. Upon completion, the memory utilized for the recomputing is free for further computations.

Abstract: Machine learning model scalability with distributed multi-layer processing is disclosed herein. A method for processing and deploying machine learning models that enhances scalability and efficiency by executing a subset of a neural network on each of a plurality of interconnected processing units. The method involves partitioning compute tasks across these processing units to reduce latency, including broadcast and reduction processes for inputs and outputs. It also includes managing the allocation of samples in a batch to specific master processing units within the distributed arrangement and synchronizing computation between fully connected layers within each processing unit. Additionally, the method implements data reduction during the transfer of data across the processing units, wherein data is accumulated with a current processing unit's partial sum as it is transferred to the destination processing unit.

Abstract: A manufacturing method of an electronic device includes: forming a conductive material layer on a substrate, the conductive material layer continuously extends from a first surface of the substrate to a second surface while passing through a side surface, wherein the side surface connects the first surface and the second surface, forming a first protection layer on the conductive material layer and patterning the conductive material layer by using the first protection layer as a mask to form an edge wire, wherein the edge wire is retracted relative to the first protection layer and forms an undercut structure, and forming a second protection layer on the substrate, wherein the second protection layer fills the undercut structure.

Abstract: This disclosure provides systems, methods, and devices for image signal processing that support high dynamic range (HDR) image processing. In a first aspect, a method of image processing includes receiving, by a processor, first image data comprising a plurality of image frames comprising at least a first image frame having a first bitwidth and a second image frame having a second bitwidth, wherein the plurality of image frames represent a same scene; and determining a processed image frame having an output bitwidth higher than the first bitwidth and higher than the second bitwidth, the processed image frame based on the plurality of image frames by combining the plurality of image frames to obtain the output bitwidth. Other aspects and features are also claimed and described.

Abstract: A digital lithography system includes adjacent scan regions, exposure units located above the scan regions, a memory, and a processing device operatively coupled to the memory. The exposure units include a first exposure unit associated with a first scan region and a second exposure unit associated with a second scan region. The processing device is to initiate a digital lithography process to pattern a substrate disposed on a stage in accordance with instructions. The processing device is to further perform a first pass of the first exposure unit over a stitching region at an interface of the first scan region and the second scan region at a first time. The processing device is to further perform a second pass of the second exposure unit over the stitching region at a second time that varies from the first time by less than forty seconds.

Abstract: A method of determining routing path for a TSN system includes determining a plurality of candidate disjoint path pairs of each of a first plurality of streams according to a network topology; initializing a plurality of final routing path pairs used for the first plurality of streams and a plurality of background streams according to a first plurality of lengths of the first plurality of candidate disjoint path pairs; selecting a plurality of temporary routing path pairs used for the first plurality of streams and the plurality of background streams according to the first plurality of parameters; updating the first plurality of parameters according to the plurality of temporary routing path pairs; and replacing the plurality of temporary routing path pairs with the plurality of final routing path pairs in response to the plurality of temporary routing path pairs being better than the plurality of final routing path pairs.

Abstract: A heat dissipation device is provided and includes: a first vapor chamber filled with a first working fluid therein and used for contacting at least one heat source; at least one heat transfer structure disposed on a side of the first vapor chamber; and a second vapor chamber filled with a second working fluid therein and connected to the first vapor chamber via the heat transfer structure, where the first working fluid absorbs heat of the heat source and then vaporizes, and the vaporized first working fluid transfers the heat to the second working fluid via the heat transfer structure.

Abstract: A method includes: providing a photomask used in extreme ultra violet (EUV) lithography; determining a bias voltage of an electron beam writer system, the bias voltage applicable to an inspection operation and a repairing operation; and performing the repairing operation on the photomask by the electron beam writer system with the bias voltage.

Abstract: A method includes: providing a photomask used in extreme ultra violet (EUV) lithography; receiving information of the photomask; determining a bias voltage of an electron beam writer system according to the information; and performing a repairing operation on the photomask by the electron beam writer system with the bias voltage.

Abstract: Embodiments of the present disclosure generally relate to lithography systems. More particularly, embodiments of the present disclosure relate to a method, a system, and a software application for a lithography process to control transmittance rate of write beams and write gray tone patterns in a single exposure operation. In one embodiment, a plurality of shots are provided by an image projection system in a lithography system to a photoresist layer. The plurality of shots exposes the photoresist layer to an intensity of light emitted from the image projection system. The local transmittance rate of the plurality of shots within an exposure area is varied to form varying step heights in the exposure area of the photoresist layer.

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.