Patents by Inventor Chih-Chun Hsu
Chih-Chun Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240121373Abstract: Disclosed are an image display method and a 3d display system. The method is adapted to the 3d display system including a 3d display device and includes the following steps. A first image and a second image are obtained by splitting an input image according to a 3d image format. Whether the input image is a 3D format image complying with the 3D image format is determined through a stereo matching processing performed on the first image and the second image. An image interweaving process is enabled to be performed on the input image to generate an interweaving image in response to determining that the input image is the 3D format image complying with the 3D image format, and the interweaving image is displayed via the 3D display device.Type: ApplicationFiled: May 10, 2023Publication date: April 11, 2024Applicant: Acer IncorporatedInventors: Kai-Hsiang Lin, Hung-Chun Chou, Wen-Cheng Hsu, Shih-Hao Lin, Chih-Haw Tan
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Patent number: 11931187Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.Type: GrantFiled: March 16, 2018Date of Patent: March 19, 2024Assignees: Chang Gung Medical Foundation Chang Gung Memorial Hospital at Keelung, Chang Gung Memorial Hospital, Linkou, Chang Gung UniversityInventors: Jiun-Jie Wang, Yi-Hsin Weng, Shu-Hang Ng, Jur-Shan Cheng, Yi-Ming Wu, Yao-Liang Chen, Wey-Yil Lin, Chin-Song Lu, Wen-Chuin Hsu, Chia-Ling Chen, Yi-Chun Chen, Sung-Han Lin, Chih-Chien Tsai
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Patent number: 11937415Abstract: A method of forming a semiconductor device includes providing a substrate including a circuit region and a well strap region, forming a mandrel extending from the circuit region to the well strap region, depositing mandrel spacers on sidewalls of the mandrel, removing the mandrel in the circuit region, while the mandrel in the well strap region remains intact, patterning the substrate with the mandrel spacers in the circuit region and the mandrel in the well strap region as an etch mask, thereby forming at least a first fin in the circuit region and a second fin in the well strap region, and epitaxially growing a first epitaxial feature over the first fin in the circuit region and a second epitaxial feature over the second fin in the well strap region. A width of the second fin is larger than a width of the first fin.Type: GrantFiled: July 27, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Chuan Yang, Kuo-Hsiu Hsu, Feng-Ming Chang, Wen-Chun Keng, Lien Jung Hung
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Publication number: 20240086612Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Inventors: Po-Hsiang HUANG, Fong-Yuan CHANG, Clement Hsingjen WANN, Chih-Hsin KO, Sheng-Hsiung CHEN, Li-Chun TIEN, Chia-Ming HSU
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Publication number: 20240085614Abstract: An anti-peep light source module includes a light source module and a viewing angle switching module. The light source module has a light source and a light guide plate (LGP) and has light emitting elements arranged along a first direction. The viewing angle switching module is located on a transmission path of an illumination beam of the light source module and includes a viewing angle limiting element and a viewing angle adjusting element configured to change a viewing angle of the illumination beam. The viewing angle limiting element has a grating structure and is located between the viewing angle adjusting element and the light source module. an included angle between an extension direction of the grating structure and the first direction is within a range from 88 degrees to 92 degrees. The anti-peep light source module and A display device achieve favorable optical performance, user experience, and production yield.Type: ApplicationFiled: September 8, 2023Publication date: March 14, 2024Applicant: Coretronic CorporationInventors: Yi-Cheng Lin, Chih-Hsuan Kuo, Sung-Chun Hsu, Ming-Hsiung Fan, Tzeng-Ke Shiau
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Publication number: 20230253390Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a base, a first system-on-chip (SOC) die, a conductive routing and a first shielding film. The first SOC die is disposed on the base. The first SOC die has a front surface and a back surface. The first SOC die includes a first inductor close to the front surface. The conductive routing is disposed on the back surface of the first SOC die. The first shielding film is disposed between the first SOC die and the conductive routing. The first shielding film covers the back surface of the first SOC die and fully overlaps the first inductor.Type: ApplicationFiled: January 13, 2023Publication date: August 10, 2023Inventors: Ruey-Bo SUN, Chih-Chun HSU, Sheng-Mou LIN
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Patent number: 10446508Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a package substrate. An integrated circuit (IC) die having a radio frequency (RF) circuit and a memory die are stacked over the package substrate. The memory die entirely covers a first surface portion of the package substrate to define a second surface portion of the package substrate exposed from the memory die, and the IC die partially covers the first surface portion and the second surface portion of the package substrate. The RF circuit includes a first sensitive device region corresponding to the second surface portion of the package substrate and a second sensitive device region corresponding to the first surface portion of the package substrate and offsetting a memory input/output (I/O) electrical path of the memory die, as viewed from a top-view perspective.Type: GrantFiled: August 22, 2017Date of Patent: October 15, 2019Assignee: MEDIATEK INC.Inventors: Sheng-Mou Lin, Chih-Chun Hsu, Wen-Chou Wu
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Patent number: 10340235Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region, a semiconductor die disposed on the package substrate in the first region, a conductive shielding element disposed on the package substrate and covering the semiconductor die, and a three-dimensional (3D) antenna. The 3D antenna includes a planar structure portion disposed on the package substrate in the second region, and a bridge structure portion above the planar structure portion and connected thereto.Type: GrantFiled: December 14, 2017Date of Patent: July 2, 2019Assignee: MEDIATEK INC.Inventors: Chih-Chun Hsu, Sheng-Mou Lin
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Patent number: 10068856Abstract: An integrated circuit apparatus includes a substrate, an IC chip disposed above the substrate, and an electromagnetic shielding layer disposed on a surface of the substrate. The IC chip includes an electromagnetic coupling device. The electromagnetic shielding layer and the electromagnetic coupling device partially overlap in a vertical projection direction of the surface of the substrate.Type: GrantFiled: May 31, 2017Date of Patent: September 4, 2018Assignee: MEDIATEK INC.Inventors: Jui-Chih Kao, Ming-Da Tsai, Yuan-Yu Fu, Chih-Chun Hsu
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Publication number: 20180108624Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region, a semiconductor die disposed on the package substrate in the first region, a conductive shielding element disposed on the package substrate and covering the semiconductor die, and a three-dimensional (3D) antenna. The 3D antenna includes a planar structure portion disposed on the package substrate in the second region, and a bridge structure portion above the planar structure portion and connected thereto.Type: ApplicationFiled: December 14, 2017Publication date: April 19, 2018Inventors: Chih-Chun HSU, Sheng-Mou LIN
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Publication number: 20180061786Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a package substrate. An integrated circuit (IC) die having a radio frequency (RF) circuit and a memory die are stacked over the package substrate. The memory die entirely covers a first surface portion of the package substrate to define a second surface portion of the package substrate exposed from the memory die, and the IC die partially covers the first surface portion and the second surface portion of the package substrate. The RF circuit includes a first sensitive device region corresponding to the second surface portion of the package substrate and a second sensitive device region corresponding to the first surface portion of the package substrate and offsetting a memory input/output (I/O) electrical path of the memory die, as viewed from a top-view perspective.Type: ApplicationFiled: August 22, 2017Publication date: March 1, 2018Inventors: Sheng-Mou LIN, Chih-Chun HSU, Wen-Chou WU
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Patent number: 9881882Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region. A semiconductor die is disposed on the package substrate in the first region. A three-dimensional (3D) antenna is disposed on the package substrate in the second region. The 3D antenna includes a planar structure portion and a bridge or wall structure portion. A molding compound encapsulates the semiconductor die and at least a portion of the 3D antenna. A conductive shielding element is inside the molding compound or partially covers the molding compound. A semiconductor package assembly having the semiconductor package is also provided.Type: GrantFiled: October 26, 2016Date of Patent: January 30, 2018Assignee: MEDIATEK INC.Inventors: Chih-Chun Hsu, Sheng-Mou Lin
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Publication number: 20180019210Abstract: An integrated circuit apparatus includes a substrate, an IC chip disposed above the substrate, and an electromagnetic shielding layer disposed on a surface of the substrate. The IC chip includes an electromagnetic coupling device. The electromagnetic shielding layer and the electromagnetic coupling device partially overlap in a vertical projection direction of the surface of the substrate.Type: ApplicationFiled: May 31, 2017Publication date: January 18, 2018Inventors: Jui-Chih Kao, Ming-Da Tsai, Yuan-Yu Fu, Chih-Chun Hsu
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Publication number: 20170194271Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region. A semiconductor die is disposed on the package substrate in the first region. A three-dimensional (3D) antenna is disposed on the package substrate in the second region. The 3D antenna includes a planar structure portion and a bridge or wall structure portion. A molding compound encapsulates the semiconductor die and at least a portion of the 3D antenna. A conductive shielding element is inside the molding compound or partially covers the molding compound. A semiconductor package assembly having the semiconductor package is also provided.Type: ApplicationFiled: October 26, 2016Publication date: July 6, 2017Inventors: Chih-Chun HSU, Sheng-Mou LIN
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Patent number: 9325063Abstract: A radiation pattern insulator and an antennae system thereof are proposed. The radiation pattern insulator includes a dielectric substrate and a plurality of radiation pattern insulation elements. The dielectric substrate allocated between a plurality of antennae includes a top surface and a bottom surface, and a normal direction of the dielectric substrate is substantially perpendicular to propagation directions of electromagnetic waves radiated from the antennae. In addition, the radiation pattern insulation elements are allocated on the top surface or the bottom surface of the dielectric substrate, or alternatively, all allocated on the top surface and the bottom surface.Type: GrantFiled: January 2, 2014Date of Patent: April 26, 2016Assignees: Industrial Technology Research Institute, National Sun Yat-sen UniversityInventors: Chun-Yih Wu, Hung-Hsuan Lin, Ken-Huang Lin, Hsin-Lung Su, Chih-Chun Hsu
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Patent number: 9235676Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) design method. The method includes (1) receiving a first layout comprising stripe patterns with a first separation and a first width; (2) receiving a second layout comprising stripe patterns with a second width narrower than the first separation, each stripe on the second layout is configured to situate between two adjacent stripes on the first layout when overlaying the first layout and the second layout; (3) performing a separation check by identifying a spacing between a stripe on the second layout and one of the two adjacent stripes on the first layout; and (4) adjusting the spacing between the stripe on the second layout and one of the two adjacent stripes on the first layout when the separation check determining the spacing is greater than a predetermined value.Type: GrantFiled: April 25, 2014Date of Patent: January 12, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chuan-Fang Su, Chih-Chun Hsu, Hsing-Wang Chen, Rung-Shiang Chen, Ching-Juinn Huang
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Publication number: 20150310156Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) design method. The method includes (1) receiving a first layout comprising stripe patterns with a first separation and a first width; (2) receiving a second layout comprising stripe patterns with a second width narrower than the first separation, each stripe on the second layout is configured to situate between two adjacent stripes on the first layout when overlaying the first layout and the second layout; (3) performing a separation check by identifying a spacing between a stripe on the second layout and one of the two adjacent stripes on the first layout; and (4) adjusting the spacing between the stripe on the second layout and one of the two adjacent stripes on the first layout when the separation check determining the spacing is greater than a predetermined value.Type: ApplicationFiled: April 25, 2014Publication date: October 29, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: CHUAN-FANG SU, CHIH-CHUN HSU, HSING-WANG CHEN, RUNG-SHIANG CHEN, CHING-JUINN HUANG
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Patent number: 9164025Abstract: A method for image sticking inspection of a light-transmissive device is disclosed. The light-transmissive device is responsive to application of a voltage to electrodes thereof to adjust light transmission characteristics. The method includes: providing light for passage through the light-transmissive device; applying a first alternating current (AC) voltage to the electrodes; applying a direct current voltage to the electrodes; and applying a second AC voltage to the electrodes, and measuring intensity of the light passing through the light-transmissive device during application of the second AC voltage.Type: GrantFiled: April 8, 2013Date of Patent: October 20, 2015Assignee: Daxin Materials Corp.Inventors: Min-Ruei Tasi, Li-Hsin Chang, Chih-Chun Hsu, Kuan-Ming Lin
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Publication number: 20140111398Abstract: A radiation pattern insulator and an antennae system thereof are proposed. The radiation pattern insulator includes a dielectric substrate and a plurality of radiation pattern insulation elements. The dielectric substrate allocated between a plurality of antennae includes a top surface and a bottom surface, and a normal direction of the dielectric substrate is substantially perpendicular to propagation directions of electromagnetic waves radiated from the antennae. In addition, the radiation pattern insulation elements are allocated on the top surface or the bottom surface of the dielectric substrate, or alternatively, all allocated on the top surface and the bottom surface.Type: ApplicationFiled: January 2, 2014Publication date: April 24, 2014Applicants: National Sun Yat-sen University, Industrial Technology Research InstituteInventors: Chun-Yih Wu, Hung-Hsuan Lin, Ken-Huang Lin, Hsin-Lung Su, Chih-Chun Hsu
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Patent number: 8643546Abstract: A radiation pattern insulator and an antennae system thereof are proposed. The radiation pattern insulator includes a dielectric substrate and a plurality of radiation pattern insulation elements. The dielectric substrate allocated between a plurality of antennae includes a top surface and a bottom surface, and a normal direction of the dielectric substrate is substantially perpendicular to propagation directions of electromagnetic waves radiated from the antennae. In addition, the radiation pattern insulation elements are allocated on the top surface or the bottom surface of the dielectric substrate, or alternatively, all allocated on the top surface and the bottom surface.Type: GrantFiled: November 20, 2009Date of Patent: February 4, 2014Assignees: Industrial Technology Research Institute, National Sun Yat-sen UniversityInventors: Chun-Yih Wu, Hung-Hsuan Lin, Ken-Huang Lin, Hsin-Lung Su, Chih-Chun Hsu