Patents by Inventor Chih Chun Wang

Chih Chun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12314954
    Abstract: The present disclosure provides a multi-factor authentication system for self-service energy replenishing and method thereof. A user may acquire a multi-factor authentication service by an application for experiencing a convenient and safe self-service energy replenishing service. During the registration stage, registration stage upon the user logging into the application of the multi-factor authentication system, the user may complete tasks of identity authentication, account setup (such as obtain a membership of the energy replenishing station), and obtain permission of use for the account, thereby enabling the user to access services provided by the multi-factor authentication service platform.
    Type: Grant
    Filed: July 5, 2024
    Date of Patent: May 27, 2025
    Inventor: Chih-Chun Wang
  • Publication number: 20240408532
    Abstract: A pre-interception device includes an input portion for a fluid to flow in, an output portion for the fluid to flow out, a plurality of diversion flow channels and a plurality of interception portions. Each diversion flow channel is in communication with the output portion and the input portion, is configured to provide turning guidance for flow of the fluid, and has a fluid lift section. The interception portions are configured to form a turbulent flow field in the fluid. The turbulent flow field can have foreign objects flowing through the diversion flow channel be captured. Accordingly, a filtering effect is achieved based on physical properties of the foreign objects. When the pre-interception device is additionally combined with a filter net to form a filtering system, the burden on the filter net is further alleviated, hence extending a service life of the filter net and reducing costs.
    Type: Application
    Filed: April 15, 2024
    Publication date: December 12, 2024
    Inventors: Chia-Lin LIN, Chih-Chun WANG
  • Patent number: 12130467
    Abstract: A backlight module comprises a back plate, a light-guiding plate arranged at the back plate and a light source module. The light-guiding plate has an incident surface and an emitting surface connected to each other. The light source module has a base board and at least one light-emitting unit. The base board is disposed at the emitting surface of the light-guiding plate. The light-emitting unit is mounted at the base board and faces the incident surface of the light-guiding plate. The base board comprises an electrically-connecting portion and at least one heat dissipation portion. The electrically-connecting portion is electrically connected to the light-emitting unit. The heat dissipation portion extends from the electrically-connecting portion toward a direction away from the light-guiding plate without being electrically connected to the light-emitting unit. A display device having the backlight module is also provided.
    Type: Grant
    Filed: December 13, 2023
    Date of Patent: October 29, 2024
    Assignee: RADIANT OPTO-ELECTRONICS CORPORATION
    Inventors: Kuan-Feng Chen, Che-Kai Chang, Jyun-Siang Chen, Chih-Chun Wang
  • Publication number: 20240272349
    Abstract: A backlight module comprises a back plate, a light-guiding plate arranged at the back plate and a light source module. The light-guiding plate has an incident surface and an emitting surface connected to each other. The light source module has a base board and at least one light-emitting unit. The base board is disposed at the emitting surface of the light-guiding plate. The light-emitting unit is mounted at the base board and faces the incident surface of the light-guiding plate. The base board comprises an electrically-connecting portion and at least one heat dissipation portion. The electrically-connecting portion is electrically connected to the light-emitting unit. The heat dissipation portion extends from the electrically-connecting portion toward a direction away from the light-guiding plate without being electrically connected to the light-emitting unit. A display device having the backlight module is also provided.
    Type: Application
    Filed: December 13, 2023
    Publication date: August 15, 2024
    Inventors: Kuan-Feng CHEN, Che-Kai CHANG, Jyun-Siang CHEN, Chih-Chun WANG
  • Patent number: 10715278
    Abstract: A system and method for operating a wireless communication node. The system configures the node to receive a signal encoded by one or more codeword sets and configures the node to remap subpackets of the incoming signal for transmission over a second communication link. Incoming signals are parsed into subpackets, and the subpackets are encoded and remapped. The encoded and/or remapped subpackets are then transmitted over a communication link.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 14, 2020
    Assignee: Purdue Research Foundation
    Inventors: David J. Love, Chih-Chun Wang
  • Publication number: 20190238263
    Abstract: A system and method for operating a wireless communication node. The system configures the node to receive a signal encoded by one or more codeword sets and configures the node to remap subpackets of the incoming signal for transmission over a second communication link. Incoming signals are parsed into subpackets, and the subpackets are encoded and remapped. The encoded and/or remapped subpackets are then transmitted over a communication link.
    Type: Application
    Filed: September 26, 2018
    Publication date: August 1, 2019
    Inventors: David J. Love, Chih-Chun Wang
  • Publication number: 20160217963
    Abstract: The present invention provides a plasma generating device comprising a high voltage driving device, an insulated substrate, and two electrode units. The present invention further provides a manufacturing method of a plasma generating device comprising the following steps of: (1) preparing an insulated substrate with a first surface and a second surface; (2) preparing two electrode units which respectively dispose one electrode unit on the first surface and the second surface, and (3) connecting the electrode with the high voltage driving device. Compared to the prior arts, the present invention provides a simpler process to manufacture the micro plasma generating device without using delicate facilities or machine tools. The present invention has advantages of lower cost and simpler manufacturing processes.
    Type: Application
    Filed: July 23, 2015
    Publication date: July 28, 2016
    Inventors: Cheng-Che Hsu, Yao-Jhen Yang, Peng-Kai Kao, Tzu-Hsuan Lin, Chih-Chun Wang
  • Patent number: 9177874
    Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an optical planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Joachim Patzer, Ardechir Pakfar, Dominic Thurmer, Chih-Chun Wang, Remi Riviere, Robert Melzer, Bastian Haussdoerfer, Martin Weisheit
  • Patent number: 9177789
    Abstract: A semiconductor process of the present invention is described as follows. A substrate is provided, and a material layer is deposited on the substrate using an organic precursor as a reactant gas. A plasma treatment is conducted immediately after depositing the material layer, wherein plasma is continuously supplied during depositing the material layer and the plasma treatment. A pump-down step is conducted.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: November 3, 2015
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chih-Chun Wang, Chun-Feng Chen
  • Publication number: 20150249008
    Abstract: A semiconductor process of the present invention is described as follows. A substrate is provided, and a material layer is deposited on the substrate using an organic precursor as a reactant gas. A plasma treatment is conducted immediately after depositing the material layer, wherein plasma is continuously supplied during depositing the material layer and the plasma treatment. A pump-down step is conducted.
    Type: Application
    Filed: May 15, 2015
    Publication date: September 3, 2015
    Inventors: CHIH-CHUN WANG, CHUN-FENG CHEN
  • Patent number: 9064691
    Abstract: A semiconductor process of the present invention is described as follows. A substrate is provided, and a material layer is deposited on the substrate using an organic precursor as a reactant gas. A plasma treatment is conducted immediately after depositing the material layer, wherein plasma is continuously supplied during depositing the material layer and the plasma treatment. A pump-down step is conducted.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: June 23, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chun Wang, Chun-Feng Chen
  • Publication number: 20150130909
    Abstract: In a method for taking three-dimensional (3D) images, a camera unit of an electrical device is utilized to shoot a same scene with a same lens focal length and focusing on different distances respectively to generate several pictures. Depth-map information of several blocks on the scene is calculated according to levels of clarity on the blocks. Offsets of the blocks of the pictures are respectively adjusted for right and left eyes according to the depth-map information of the blocks to generate at least one 3D image. The present invention also discloses an electrical device for taking 3D images and a non-transitory computer-readable storage medium for storing the method for taking a 3D image.
    Type: Application
    Filed: February 20, 2014
    Publication date: May 14, 2015
    Applicant: Institute for Information Industry
    Inventors: Jia-Huang Tang, Ruen-Rone Lee, Chih-Chun Wang
  • Publication number: 20150064812
    Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an organic planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 5, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Joachim Patzer, Ardechir Pakfar, Dominic Thurmer, Chih-Chun Wang, Remi Riviere, Robert Melzer, Bastian Haussdoerfer, Martin Weisheit
  • Patent number: 8350334
    Abstract: A stress film forming method is used in a fabrication process of a semiconductor device. Firstly, a substrate is provided, wherein a first-polarity-channel MOSFET and a second-polarity-channel MOSFET are formed on the substrate. Then, at least one deposition-curing cycle process is performed to form a cured stress film over the first-polarity-channel MOSFET and the second-polarity-channel MOSFET. Afterwards, an additional deposition process is performed form a non-cured stress film on the cured stress film, wherein the cured stress film and the non-cured stress film are collectively formed as a seamless stress film.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: January 8, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Min Wang, An-Chi Liu, Hsin-Hsing Chen, Chih-Chun Wang
  • Publication number: 20120313181
    Abstract: A stress film forming method is used in a fabrication process of a semiconductor device. Firstly, a substrate is provided, wherein a first-polarity-channel MOSFET and a second-polarity-channel MOSFET are formed on the substrate. Then, at least one deposition-curing cycle process is performed to form a cured stress film over the first-polarity-channel MOSFET and the second-polarity-channel MOSFET. Afterwards, an additional deposition process is performed form a non-cured stress film on the cured stress film, wherein the cured stress film and the non-cured stress film are collectively formed as a seamless stress film.
    Type: Application
    Filed: June 13, 2011
    Publication date: December 13, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Min Wang, An-Chi Liu, Hsin-Hsing Chen, Chih-Chun Wang
  • Publication number: 20120040535
    Abstract: A semiconductor process of the present invention is described as follows. A substrate is provided, and a material layer is deposited on the substrate using an organic precursor as a reactant gas. A plasma treatment is conducted immediately after depositing the material layer, wherein plasma is continuously supplied during depositing the material layer and the plasma treatment. A pump-down step is conducted.
    Type: Application
    Filed: August 13, 2010
    Publication date: February 16, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chun Wang, Chun-Feng Chen
  • Patent number: 7872292
    Abstract: A capacitance dielectric layer is provided. The capacitance dielectric layer includes a first dielectric layer, a second dielectric layer and a silicon nitride stacked layer. The silicon nitride stacked layer is disposed between the first dielectric layer and the second dielectric layer. The structure of the capacitance dielectric layer permits an increase in the capacitance per unit area by decreasing the thickness of the capacitance dielectric layer and eliminates the problems of having a raised leakage current and a diminished breakdown voltage.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: January 18, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chun Wang, Hsin-Hsing Chen, Yu-Ho Chiang
  • Publication number: 20080113481
    Abstract: A capacitance dielectric layer is provided. The capacitance dielectric layer includes a first dielectric layer, a second dielectric layer and a silicon nitride stacked layer. The silicon nitride stacked layer is disposed between the first dielectric layer and the second dielectric layer. The structure of the capacitance dielectric layer permits an increase in the capacitance per unit area by decreasing the thickness of the capacitance dielectric layer and eliminates the problems of having a raised leakage current and a diminished breakdown voltage.
    Type: Application
    Filed: January 15, 2008
    Publication date: May 15, 2008
    Inventors: Chih-Chun Wang, Hsin-Hsing Chen, Yu-Ho Chiang
  • Publication number: 20080067145
    Abstract: A method of recycling dummy wafer is provided. The dummy wafer has at least one low-k dielectric material layer formed thereon. A treatment process is performed to the low-k dielectric material layer on the dummy wafer so that a component or impurity in the low-k dielectric material layer reacts to form a volatile substance. A wet etching process is performed to remove the low-k dielectric material layer.
    Type: Application
    Filed: September 14, 2006
    Publication date: March 20, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chun Wang, Chia-Pin Lee, Chun-Yuan Wu, Hsien-Che Teng, Hsin-Hsing Chen, Yu-Cheng Lin
  • Publication number: 20070196977
    Abstract: A capacitance dielectric layer is provided. The capacitance dielectric layer includes a first dielectric layer, a second dielectric layer and a silicon nitride stacked layer. The silicon nitride stacked layer is disposed between the first dielectric layer and the second dielectric layer. The structure of the capacitance dielectric layer permits an increase in the capacitance per unit area by decreasing the thickness of the capacitance dielectric layer and eliminates the problems of having a raised leakage current and a diminished breakdown voltage.
    Type: Application
    Filed: February 21, 2006
    Publication date: August 23, 2007
    Inventors: Chih-Chun Wang, Hsin-Hsing Chen, Yu-Ho Chiang