Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.

Abstract: The disclosure provides an electronic device with a vibration function and a vibration driving method. The electronic device includes a processor and an audio player. The processor outputs an audio signal according to an application program, and executes an audio analysis module to analyze the audio signal. The audio player is coupled to the processor, and receives the audio signal. When the audio analysis module determines that the audio signal has a loudness with an audio frequency lower than a default frequency threshold according to an audio frequency distribution of the audio signal, the audio analysis module outputs a vibration drive signal according to the loudness of the audio signal.

Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

Abstract: A method for determining a standard depth value of a marker includes obtaining a maximum depth value of the marker. A reference depth value of the marker is obtained based on a depth image of the marker, and a Z-axis coordinate value of the marker is obtained based on a color image of the marker. When the reference depth value and the Z-axis coordinate value are both less than the maximum depth value, and a difference between the reference depth value and the Z-axis coordinate value is not greater than 0, the depth reference value is set as the standard depth value of the marker; and when the difference is greater than 0, the Z-axis coordinate value is set as the standard depth value of the marker.

Abstract: A semiconductor device includes one or more active semiconductor components, wherein a front side is defined over the semiconductor substrate and a back side is defined beneath the semiconductor substrate. A front side power rail is formed at the front side of the semiconductor device and is configured to receive a first reference power voltage. First and second back side power rails are formed on the back side of the semiconductor substrate and are configured to receive corresponding second and third reference power voltages. The first, second and third reference power voltages are different from each other.

Abstract: A semiconductor process system includes a process chamber. The process chamber includes a wafer support configured to support a wafer. The system includes a bell jar configured to be positioned over the wafer during a semiconductor process. The interior surface of the bell jar is coated with a rough coating. The rough coating can include zirconium.

Abstract: An integrated circuit includes first-type transistors aligned within a first-type active zone, second-type transistors aligned within a second-type active zone, a first power rail and a second power rail extending in a first direction. A first distance between the long edge of the first power rail and the first alignment boundary of the first-type active zone is different from a second distance between the long edge of the second power rail and the first alignment boundary of the second-type active zone. Each of the first distance and the second distance is along a second direction which is perpendicular to the first direction.

Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: A system including a processor configured to perform generating a plurality of different layout blocks; selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit; combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit. Each of the plurality of layout blocks satisfies predetermined design rules and includes at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: A brain tumor types distinguish system includes an image outputting device and a server computing device. The image outputting device outputs at least three brain images captured from the position of a brain tumor. The server computing device pre-stores a plurality of distinguish pathways corresponding to different types of brain tumors. The server computing device includes an image receiving module, an image pre-processing module, a data comparison module and a distinguish module. The image receiving module receives the brain images. The image pre-processing module pre-processes the brain images to obtain corresponding processed images thereof. The data comparison module compares the brain images and the processed images with the distinguish pathways to obtain at least three comparison results. The distinguish module statistically analyzes the comparison results to obtain a distinguish result.

Abstract: A benign tumor development trend assessment system includes an image outputting device and a server computing device. The image outputting device outputs first/second images captured from the same position in a benign tumor. The server computing device includes an image receiving module, an image pre-processing module, a target extracting module, a feature extracting module and a trend analyzing module. The image receiving module receives the first/second images. The image pre-processing module pre-processes the first/second images to obtain first/second local images. The target extracting module automatically detects and delineates tumor regions from the first/second local images to obtain first/second region of interest (ROI) images. The feature extracting module automatically identifies the first/second ROI images to obtain at least one first/second features. The trend analyzing module analyzes the first/second features to obtain a tumor development trend result.

Abstract: A method for enhancing an accuracy of a benign tumor development trend assessment system includes: a first processing procedure, an image captured before the treatment is inputted to and be processed by a server computing device of the benign tumor development trend assessment system to obtain a first processing result; a second processing procedure, the images captured before and in at least one period after the treatment are inputted to and processed by the server computing device to obtain a second processing result; a trend analyzing procedure, the trend analyzing module of the server computing device analyzes the first processing result, the second processing result and the trend pathways to obtain a tumor development trend result; and a storing procedure, the first processing result, the second processing result and the tumor development trend result are transformed to an individual trend pathway which is stored in the trend analyzing module.

Abstract: A benign tumor development trend assessment system includes an image outputting device and a server computing device. The image outputting device outputs first/second images captured from the same position in a benign tumor. The server computing device includes an image receiving module, an image pre-processing module, a target extracting module, a feature extracting module and a trend analyzing module. The image receiving module receives the first/second images. The image pre-processing module pre-processes the first/second images to obtain first/second local images. The target extracting module automatically detects and delineates tumor regions from the first/second local images to obtain first/second region of interest (ROI) images. The feature extracting module automatically identifies the first/second ROI images to obtain at least one first/second features. The trend analyzing module analyzes the first/second features to obtain a tumor development trend result.