Abstract: Aspects of the present disclosure provide a method for controlling a processing device to execute an application that runs on a neural network (NN). The processing device can include a plurality of processing units that are arranged in a network-on-chip (NoC) architecture. For example, the method can include obtaining compiler information relating the application and the NoC, controlling the processing device to employ a first routing scheme to process the application when the compiler information does not meet a predefined requirement, and controlling the processing device to employ a second routing scheme to process the application when the compiler information meets the predefined requirement.

Abstract: Aspects of the present disclosure provide a method for controlling a processing device to execute an application that employs a neural network (NN). The processing device includes a plurality of processing units arranged in a network-on-chip (NoC) to which the NN is mapped. For example, the method can include obtaining compiler information. The compiler information can include computing loads of the application on the processing units. The computing loads can relate a dataflow type of the NN. The method can also include determining a scaling factor for computing time of each of the processing units based on the computing loads, adjusting the computing time of the processing units based on the scaling factors, and enabling the processing units to perform their respective tasks of the application within their respective adjusted computing time.

Abstract: An analog circuit is calibrated to perform neural network computing. Calibration input is provided to a pre-trained neural network that includes at least a given layer having pre-trained weights stored in the analog circuit. The analog circuit performs tensor operations of the given layer using the pre-trained weights. Statistics of calibration output from the analog circuit is calculated. Normalization operations to be performed during neural network inference are determined. The normalization operations incorporate the statistics of the calibration output and are performed at a normalization layer that follows the given layer. A configuration of the normalization operations is written into memory while the pre-trained weights stay unchanged.

Abstract: A deep learning accelerator (DLA) includes processing elements (PEs) grouped into PE groups to perform convolutional neural network (CNN) computations, by applying multi-dimensional weights on an input activation to produce an output activation. The DLA also includes a dispatcher which dispatches input data in the input activation and non-zero weights in the multi-dimensional weights to the processing elements according to a control mask. The DLA also includes a buffer memory which stores the control mask which specifies positions of zero weights in the multi-dimensional weights. The PE groups generate output data of respective output channels in the output activation, and share a same control mask specifying same positions of the zero weights.

Abstract: A graphics accelerator device offloads the workload of a graphics processing unit (GPU) by performing image composition and other specialized functions. The graphics accelerator device includes a rasterization module to rasterize a set of primitives to a set of pixels and generate information of the set of pixels. The graphics accelerator device also includes intra-process module to retrieve pixel values from a memory according to the information received from the rasterization module, perform mathematical calculations on the pixel values, and generate one or more processed image layers. The graphics accelerator device further includes an inter-process module to composite the one or more processed image layers received from the intra-process module with other image layers retrieved from the memory, and output a composited image to a display.

Abstract: A graphics accelerator device offloads the workload of a graphics processing unit (GPU) by performing image composition and other specialized functions. The graphics accelerator device includes a rasterization module to rasterize a set of primitives to a set of pixels and generate information of the set of pixels. The graphics accelerator device also includes intra-process module to retrieve pixel values from a memory according to the information received from the rasterization module, perform mathematical calculations on the pixel values, and generate one or more processed image layers. The graphics accelerator device further includes an inter-process module to composite the one or more processed image layers received from the intra-process module with other image layers retrieved from the memory, and output a composited image to a display.

Abstract: A graphic processing system and a method of graphic processing are provided. The graphic processing system has a collector, a plurality of slots, a scheduler, an arbiter and at least an arithmetic logic unit (ALU). The collector is configured to group a plurality of workitems into elementary wavefronts. Each of the elementary wavefronts comprises workitems configured to execute the same kernel code. The scheduler is configured to allocate the elementary wavefronts to the slots. Two or more of the elementary wavefronts exist at one slot to form one of a plurality of macro wavefronts. The arbiter is configured to select one of the macro wavefronts. The ALU is configured to execute workitems of at least an elementary wavefront of the selected macro wavefront and output results of execution of the workitems.

Abstract: A graphic processing system and a method of graphic processing are provided. The graphic processing system has a collector, a plurality of slots, a scheduler, an arbiter and at least an arithmetic logic unit (ALU). The collector is configured to group a plurality of workitems into elementary wavefronts. Each of the elementary wavefronts comprises workitems configured to execute the same kernel code. The scheduler is configured to allocate the elementary wavefronts to the slots. Two or more of the elementary wavefronts exist at one slot to form one of a plurality of macro wavefronts. The arbiter is configured to select one of the macro wavefronts. The ALU is configured to execute workitems of at least an elementary wavefront of the selected macro wavefront and output results of execution of the workitems.

Abstract: The water provisioning system mainly contains a selection switch, a water volume switch, a human-machine interface (HMI), a RO waste water recycling device, an electromagnetic valve, a RO water purification device, an antichlor device, an aeration pipe assembly, a first ozone module, and a second ozone module. The selection switch selects a type of water to use. The RO water purification device filters water from a low-temperature water source, stores purified water in a storage barrel, and provides high-quality drinking water. The 70% water from the RO water purification process that fails the drinking water standard is recycled through the RO waste water recycling device. The low-temperature water source is connected to an antichlor device and the water is therefore dechlorinated. The first and second ozone modules are used to produce ozonated water and to release ozone through the aeration pipe assembly into the kitchen cabinet for deodorization and sterilization.

Abstract: The water provisioning system mainly contains a selection switch, a water volume switch, a human-machine interface (HMI), a RO waste water recycling device, an electromagnetic valve, a RO water purification device, an antichlor device, a aeration pipe assembly, a first ozone module, and a second ozone module. The selection switch selects a type of water to use. The RO water purification device filters water from a low-temperature water source, stores purified water in a storage barrel, and provides high-quality drinking water. The 70% water from the RO water purification process that fails the drinking water standard is recycled through the RO waste water recycling device. The low-temperature water source is connected to a antichlor device and the water is therefore dechlorinated. The first and second ozone modules are used to produce ozonated water and to release ozone through the aeration pipe assembly into the kitchen cabinet for deodorization and sterilization.

Abstract: An automatic ozone water output device includes a faucet unit, at least one water inlet pipe, and an ozone generator. The faucet unit will automatically detect the presence of a user to output water. The water inlet pipe having a Venturi section connects the faucet unit and a water source. An ozone generating device having a pressure-sensitive activator is kept in a concealed space or a sheltered location, such as in the area under a basin or a sink. When water flows through the Venturi pipe, a negative pressure is developed and sensed by the pressure-sensitive activator. In response, the pressure-sensitive activator activates the ozone generator, thereby causing the mixing of ozone with the discharged water.

Abstract: A microprocessor and main board mounting arrangement, which includes a computer main board, at least one socket respectively mounted on the computer main board, at least one microprocessor adapter respectively mounted on the at least one socket, said at least one microprocessor adapter each holding a respective microprocessor, for example, a Desktop Celeron CPU, a Mobile Celeron or Mobile Pentium II CPU, for enabling the respective microprocessor to be electrically connected to the computer main board, each microprocessor adapter having a voltage converter for converting output power supply of the computer main board into the necessary working voltage for the microprocessor.