Patents by Inventor Chih-Chung Lin

Chih-Chung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11515213
    Abstract: A method for forming a semiconductor device. A substrate having a first region and a second region surrounding the first region is provided. The first region includes a first active area and a first gate. A dummy pattern is disposed on the substrate within the second region around a perimeter of the first region. A resist pattern masks the second region and includes an opening that exposes the first region. An ion implantation process is performed to implant dopants through the opening into the first active area not covered by the first gate within the first region, thereby forming doped regions in the first active area. A resist stripping process is performed to remove the resist pattern by using a sulfuric acid-hydrogen peroxide mixture (SPM) solution at a temperature that is higher than or equal to 120˜190 degrees Celsius. The substrate is subjected to a cleaning process.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: November 29, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chung Chen, Po-Chang Lin, Huang-Ren Wei, Wei-Lun Chou
  • Publication number: 20220376393
    Abstract: A multi-band antenna includes a lower grounding portion, a feed-in portion, a feeding point, an upper grounding portion, a first extending portion, a second extending portion, a third extending portion, a fourth extending portion, a fifth extending portion, a first branch, a second branch, a third branch and a loop portion. The feed-in portion, the first extending portion, the second extending portion, the third extending portion, the fourth extending portion and the first branch form a first radiation portion. The feed-in portion, the first extending portion, the second extending portion, the third extending portion, the fifth extending portion and the second branch form a second radiation portion. The feed-in portion, the first extending portion, the second extending portion and the third branch form a third radiation portion.
    Type: Application
    Filed: April 20, 2022
    Publication date: November 24, 2022
    Inventors: MING-JU LIN, CHIH-CHUNG WANG, LAN-YUNG HSIAO, SHAO-KAI SUN
  • Publication number: 20220368016
    Abstract: A multi-band antenna includes a grounding portion, a feed-in portion, a feeding point, a first radiation portion, a second radiation portion, a third radiation portion and a fourth radiation portion. The feed-in portion has a first end edge, a second end edge, a first side edge and a second side edge. The feeding point is disposed at the feed-in portion. The first radiation portion is extended from the grounding portion. The second radiation portion is extended from the second end edge. The third radiation portion is extended from the first end edge. The fourth radiation portion is extended from an upper portion of the first end edge and an upper portion of the second end edge.
    Type: Application
    Filed: January 19, 2022
    Publication date: November 17, 2022
    Inventors: MING-JU LIN, LAN-YUNG HSIAO, CHIH-CHUNG WANG, SHAO-KAI SUN
  • Publication number: 20220367559
    Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Ying Liao, Huai-jen Tung, Chih Wei Sung, Po-Zen Chen, Yu-chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, Tsun-Kai Tsao, Yung-Lung Yang
  • Patent number: 11499219
    Abstract: A method of fabricating a thin film with a varying thickness includes the steps of providing a shadow mask with an opening, providing a carrier plate, arranging a substrate on the carrier plate, and coating the substrate through the opening whilst rotating the carrier plate relative to the shadow mask. A plurality of zones of the substrates is swept and exposed from arcuate portions of the opening per each turn by a plurality of predetermined exposure times, respectively. The varying thickness of the thin film corresponds to variation of the predetermined exposure times.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: November 15, 2022
    Assignee: National Chiao Tung University
    Inventors: Cheng-Sheng Huang, Chi-Yung Hsieh, Yu-Chi Lin, Chih-Chung Wu, Chi-Fang Huang
  • Patent number: 11502123
    Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Keng-Ying Liao, Huai-Jen Tung, Chih Wei Sung, Po-zen Chen, Yu-Chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, Tsun-kai Tsao, Yung-Lung Yang
  • Publication number: 20220359511
    Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
  • Publication number: 20220359606
    Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Keng-Ying Liao, Huai-jen Tung, Chih Wei Sung, Po-zen Chen, Yu-chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, S.S. Wang
  • Patent number: 11495681
    Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: November 8, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Po Hsiung, Ching-Chung Yang, Shan-Shi Huang, Shin-Hung Li, Nien-Chung Li, Wen-Fang Lee, Chiu-Te Lee, Chih-Kai Hsu, Chun-Ya Chiu, Chin-Hung Chen, Chia-Jung Hsu, Ssu-I Fu, Yu-Hsiang Lin
  • Publication number: 20220350235
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Application
    Filed: June 30, 2022
    Publication date: November 3, 2022
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Publication number: 20220328420
    Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 13, 2022
    Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
  • Publication number: 20220328627
    Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.
    Type: Application
    Filed: August 16, 2021
    Publication date: October 13, 2022
    Inventors: Jen-Hong Chang, Yi-Hsiu Liu, You-Ting Lin, Chih-Chung Chang, Kuo-Yi Chao, Jiun-Ming Kuo, Yuan-Ching Peng, Sung-En Lin, Chia-Cheng Chao, Chung-Ting Ko
  • Publication number: 20220319993
    Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer over a substrate, forming a metal layer in the first dielectric layer, forming an etch stop layer on a surface of the first dielectric layer and the metal layer, removing portions of the metal layer and the etch stop layer to form a recess in the metal layer, and forming a tungsten plug in the recess. The recess is spaced apart from a bottom surface of the etch stop layer.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 6, 2022
    Inventors: Chih-Hsuan LIN, Hsi Chung CHEN, Ji-Ling WU, Chih-Teng LIAO
  • Publication number: 20220297255
    Abstract: An air guider disposed in a grinding machine tool. The grinding machine tool comprises a casing and a motor disposed in the casing. The casing comprises a head for disposing the motor and a body formed with at least one air inlet. The air guider comprises a main body, and an ascending diversion portion integrally formed with the main body, the main body is disposed at a junction between the head and the body, the ascending diversion portion comprises a main guide surface to guide a first heat dissipation airflow entering from the air inlet to flow toward a top of the motor, and two auxiliary guide surfaces respectively disposed on two sides of the main guide surface to generate a second heat dissipation airflow.
    Type: Application
    Filed: April 20, 2022
    Publication date: September 22, 2022
    Inventors: Ding-Yao CHENG, Chih-Chung LIN, Yu-Fan WEN, Wen-Hsien SU
  • Publication number: 20220297254
    Abstract: A grinding machine tool for reducing hotness of a casing, includes a casing and a drive assembly. The casing is divided into a head and a body; includes casing parts; includes an air inlet provided on the body and an air outlet provided on a side of the head; and forms a motor cover on the head, and the motor cover does not contact the casing parts to form an airflow passage in the casing. The drive assembly includes a circuit board, a motor placed into the motor cover, and an airflow generating member rotating synchronously with the motor. When the airflow generating member rotates, it generates a first heat dissipation airflow passing through the airflow passage and dissipating heat of the circuit board and the head, and a second heat dissipation airflow dissipating heat on a side of the motor facing the airflow generating member.
    Type: Application
    Filed: March 18, 2021
    Publication date: September 22, 2022
    Inventors: Ding-Yao CHENG, Chih-Chung LIN, Yu-Fan WEN, Wen-Hsien SU
  • Publication number: 20220294413
    Abstract: A signal filter includes a notch filter and a wideband filter. The notch filter is configured to perform a band-rejection filtering operation according to a band-rejection filtering property. The wideband filter is coupled to the notch filter, and is configured to perform a wideband filtering operation according to a wideband filtering property. The band-rejection filtering property includes a first cutoff frequency, a frequency bandwidth, a relatively high quality factor and a relatively low coupling coefficient. The wideband filtering property includes a second cutoff frequency, a relatively low quality factor and a relatively high coupling coefficient. The first and the second cutoff frequencies have a frequency difference therebetween. A ratio of the frequency difference to the frequency bandwidth is within a preset ratio range being from 2.5% to 20%.
    Type: Application
    Filed: March 8, 2022
    Publication date: September 15, 2022
    Applicant: TAI-SAW Technology Co., Ltd.
    Inventors: Shih-Meng Lin, Fu-Kuo Yu, Chih-Chung Hsiao
  • Publication number: 20220270886
    Abstract: In a method of manufacturing a semiconductor device, a mask pattern is formed over a target layer to be etched, and the target layer is etched by using the mask pattern as an etching mask. The etching is performed by using an electron cyclotron resonance (ECR) plasma etching apparatus, the ECR plasma etching apparatus includes one or more coils, and a plasma condition of the ECR plasma etching is changed during the etching the target layer by changing an input current to the one or more coils.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 25, 2022
    Inventors: En-Ping LIN, Yu-Ling KO, I-Chung WANG, Yi-Jen CHEN, Sheng-Kai JOU, Chih-Teng LIAO
  • Patent number: 11417511
    Abstract: A method for drying a wafer at room temperature includes a cleaning step, a reacting step and a pressure releasing step. The cleaning step includes putting a processing workpiece into a cleaning solvent. The reacting step includes putting the processing workpiece along with the cleaning solvent into a reaction chamber, implanting a supercritical fluid into the reaction chamber, and increasing a pressure of the reaction chamber to dissolve the cleaning solvent in the supercritical fluid. A critical temperature of the supercritical fluid is below room temperature. The pressure releasing step includes releasing the pressure of the reaction chamber and discharging the supercritical fluid together with the cleaning solvent out of the reaction chamber, after completely dissolving the cleaning solvent in the supercritical fluid.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: August 16, 2022
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Ting-Chang Chang, Chih-Cheng Yang, Wen-Chung Chen, Chuan-Wei Kuo, Pei-Yu Wu, Chun-Chu Lin
  • Patent number: 11406476
    Abstract: An improved manual oral cavity expansion device comprising a fixing element with one end connected with a first holding element, and another end forming an accommodating portion protrudingly disposed with a pivoting portion; at least one linkage element disposed on the fixing element; a rotating element accommodated in an accommodating space of the accommodating portion and sleeved on the pivoting portion; a movable element with one end connected with a second holding element, and another end forming a movable portion correspondingly disposed in the accommodating space and sleeved on the pivoting portion; and an expansion unit. An outer circumference of the rotating element is arranged with a plurality of tooth elements in a row, and one end of the linkage element contacts the tooth elements. The expansion unit has a first expansion arm connected to the accommodating portion and a second expansion arm connected to the movable portion.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: August 9, 2022
    Assignee: JANMAN PRECISION INDUSTRY CO., LTD.
    Inventors: Chieh-Mao Lin, Chih-Chung Hu, Yi-Chian Wang
  • Patent number: 11406022
    Abstract: A method of fabricating a substrate having a through via includes: providing a carrier board having a release layer thereon; attaching the substrate onto the carrier board via the release layer; applying a light beam to the substrate to form a first blind hole in the substrate, wherein the first blind hole penetrates a first surface and a second surface of the substrate; performing an enlargement process on the first blind hole to form a second blind hole; forming a through via in the second blind hole; and performing a de-bonding process to release the substrate having a through via from the carrier board.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: August 2, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-I Wu, Shih-Ming Lin, Pin-Hao Hu, Yu-Chung Lin, Hsin-Yu Chang, Fu-Lung Chou, Chien-Jung Huang