Abstract: A pixel electrode structure includes a transparent substrate, a data line, a common line, a first array pixel, and a second array pixel disposed on the transparent substrate. The first/second array pixels respectively include a thin film transistor, a pixel electrode, and a gate line, and the common line is disposed at a lateral side of the gate line. A first via hole and a second via hole are respectively disposed on common line and in contact with an extending portion of the first thin film transistor and an extending portion of the second thin film transistor. A dummy line is disposed at a side of the data line, and a third via hole is disposed both on the dummy line and on the common line. The present invention can not only increase the aperture ratio of the pixel, but have a better stability of the common voltage signal.

Abstract: A thin film transistor structure of a pixel is provided. In the present invention, a first metal layer serves as a gate electrode, and the gate electrode includes an extending gate electrode portion. A second metal layer includes a drain electrode partially and respectively overlapping the gate electrode and the gate electrode portion with the amorphous silicon layer interposed therebetween so as to form a first parasitic capacitor and a second parasitic capacitor. The total capacitance of the first parasitic capacitor and the second parasitic capacitor is invariable to withstand deviation caused by vibration of the machine in the photolithographic process, so that undesired effects in the liquid crystal display panel such as mura and flicker can be reduced.

Abstract: An array substrate of a fringe field switching (FFS) mode liquid crystal display (LCD) panel and manufacturing method thereof are provided. The gate electrodes and the common electrode of the FFS mode LCD panel are formed on the array substrate by the same photolithographic process, and the common electrode, the gate lines and the gate electrodes are disposed on the same layer.

Abstract: A pixel structure includes a scan line, a data line, a gate electrode electrically connected to the scan line, a semiconductor layer disposed on the gate electrode, a drain electrode, an extending electrode, and a pixel electrode. The scan line and the data line cross each other, and are insulated. The drain electrode includes a contact part disposed outside the gate electrode, an electrode part disposed on the semiconductor pattern and a connecting part extending from the contact part along a direction to connect the electrode part, and partially overlapping the gate electrode. The pixel electrode is connected to the contact part. The extending electrode is connected to the scan line. A first end of the extending electrode points to the semiconductor layer along the direction, and overlaps the drain electrode. A first width of the connecting part is equal to the second width of the extending electrode.

Abstract: A system for display images comprising a thin film transistor array substrate is disclosed. The system for display images comprises a substrate having a pixel area, a source/drain region overlying the substrate within an active layer in the pixel area, a bottom electrode overlying the substrate in the pixel area, a top electrode overlying the bottom electrode, a first dielectric layer disposed on the active layer, a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer is disposed between the bottom electrode and the top electrode and a gate disposed overlying the active layer, wherein the first and second dielectric layers are interposed between the gate and the active layer.

Abstract: A pixel array includes scan lines extended along a row direction in a zigzag manner, data lines extended along a column direction, and pixels connected the scan lines and the data lines. Each pixel arranged in nth row includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first transistor and a first pixel electrode. A first gate electrode and a first drain electrode of the first transistor are respectively connected to the (n+1)th scan line and the first pixel electrode. A second sub-pixel includes a second transistor and a second pixel electrode. A second gate electrode and a second drain electrode of the second transistor are respectively connected to the nth scan line and the second sub-pixel electrode. A first source electrode of the first transistor and a second source electrode of the second transistor are connected to the same data line.

Abstract: A pixel structure includes a scan line, a data line, a gate electrode electrically connected to the scan line, a semiconductor layer disposed on the gate electrode, a drain electrode, an extending electrode, and a pixel electrode. The scan line and the data line cross each other, and are insulated. The drain electrode includes a contact part disposed outside the gate electrode, an electrode part disposed on the semiconductor pattern and a connecting part extending from the contact part along a direction to connect the electrode part, and partially overlapping the gate electrode. The pixel electrode is connected to the contact part. The extending electrode is connected to the scan line. A first end of the extending electrode points to the semiconductor layer along the direction, and overlaps the drain electrode. A first width of the connecting part is equal to the second width of the extending electrode.

Abstract: A pixel array includes scan lines extended along a row direction in a zigzag manner, data lines extended along a column direction, and pixels connected the scan lines and the data lines. Each pixel arranged in nth row includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first transistor and a first pixel electrode. A first gate electrode and a first drain electrode of the first transistor are respectively connected to the (n+1)th scan line and the first pixel electrode. A second sub-pixel includes a second transistor and a second pixel electrode. A second gate electrode and a second drain electrode of the second transistor are respectively connected to the nth scan line and the second sub-pixel electrode. A first source electrode of the first transistor and a second source electrode of the second transistor are connected to the same data line.

Abstract: A pixel structure includes a scan line, a data line, a gate electrode, a semiconductor layer, a source electrode, a drain electrode including a comb-shaped part surrounding the source electrode and a connecting part, and a pixel electrode electrically connected to the drain electrode. The scan line and the data line are arranged intersectedly and electrically insulated from each other. At least a portion of the source electrode and the drain electrode are disposed on the semiconductor layer. At least one branch of the comb-shaped part extends outside one side of the gate electrode to form a protrusion part. The connecting part extends from the comb-shaped part beyond the other side of the gate electrode. The protrusion part and the connecting part aligned with the margin of the gate electrode have a first width and a third width respectively, wherein the first width substantially equals to the third width.

Abstract: A pixel structure including a substrate, a scan line, a data line, a first and a second switching device, a first and a second pixel electrode, a first and a second bended pixel electrode, a first and a second connecting conductive layer, and a first and a second common line is provided. The scan line and data line demarcate a first and a second areas on the substrate, and the scan line is located between the two areas. The first and second switching devices are electrically connected to the scan line and the data line and are also electrically connected to the first and second pixel electrodes on the first and second areas respectively. The first and second bended pixel electrodes on the second and first areas are electrically connected to the first and second pixel electrodes through the first and second connecting conductive layers on the scan line respectively.

Abstract: A pixel structure suitable for being disposed on a substrate includes a thin film transistor (TFT), a first pixel electrode, a second pixel electrode, a scan line and a data line. The TFT disposed on the substrate includes a gate, a source, a first drain and a second drain. A main TFT is formed by the gate, the source and the first drain. A sub-thin film transistor (sub-TFT) is formed by the gate, the first drain and the second drain. The first pixel electrode is electrically connected to the first drain, and a portion of the first drain extends between the second pixel electrode and the substrate to form capacitor-coupling electrode. The second pixel electrode is electrically connected to the second drain of the sub-TFT. The scan line is disposed on the substrate and electrically connected to the gate, and the data line is electrically connected to the source.

Abstract: A pixel circuit for a liquid crystal display panel includes a capacitor unit, a voltage-regulating mechanism, a first switching member, and a second switching member. The liquid crystal display panel includes a plurality of scan lines and data lines. The voltage-regulating mechanism is coupled to the first and second liquid crystal capacitors thereby enabling the first and second liquid crystal capacitors to be configured with different voltages when a voltage is applied to the capacitor unit. The first switching member is coupled to the capacitor unit, one of two corresponding scan lines, and one of two corresponding data lines. The second switching member is coupled to the second liquid crystal capacitor, the other of two corresponding scan lines.

Abstract: A pixel electrode structure includes a transparent substrate, a data line, a common line, a first array pixel, and a second array pixel disposed on the transparent substrate. The first/second array pixels respectively include a thin film transistor, a pixel electrode, and a gate line, and the common line is disposed at a lateral side of the gate line. A first via hole and a second via hole are respectively disposed on common line and in contact with an extending portion of the first thin film transistor and an extending portion of the second thin film transistor. A dummy line is disposed at a side of the data line, and a third via hole is disposed both on the dummy line and on the common line. The present invention can not only increase the aperture ratio of the pixel, but have a better stability of the common voltage signal.

Abstract: The present invention provides a display panel including a plurality of dual-gate pixel units connected to each other through data lines, gate lines and common lines. Each dual-gate pixel unit includes a first pixel and a second pixel respectively connected to a first gate line and a second gate line, and shares a common line and a data line. The first pixel and the second pixel are respectively disposed at two opposite sides of the common line, and they are also respectively disposed at two opposite sides of the first data line and the second gate line. The data lines transfer data signals into pixels, and the gate lines control the pixels to receive the data signals. The present invention raises an aperture ratio of each pixel of the display panel, and reduces the probability of the gate line and the common line being short-circuited.

Abstract: A thin film transistor structure of a pixel is provided. In the present invention, a first metal layer serves as a gate electrode, and the gate electrode includes an extending gate electrode portion. A second metal layer includes a drain electrode partially and respectively overlapping the gate electrode and the gate electrode portion with the amorphous silicon layer interposed therebetween so as to form a first parasitic capacitor and a second parasitic capacitor. The total capacitance of the first parasitic capacitor and the second parasitic capacitor is invariable to withstand deviation caused by vibration of the machine in the photolithographic process, so that undesired effects in the liquid crystal display panel such as mura and flicker can be reduced.

Abstract: A pixel structure suitable for being disposed on a substrate is provided. The pixel structure includes a scan line, a data line, a thin film transistor (TFT), a primary pixel electrode, and at least one secondary pixel electrode. The scan line and the data line are disposed on the substrate. The TFT is disposed on the substrate and is electrically connected to the scan line and the data line. The primary pixel electrode is electrically connected to a drain electrode of the TFT through a contact hole. The secondary pixel electrode is disposed above the drain electrode and the drain electrode is electrically coupled to the secondary pixel electrode. Besides, a liquid crystal display (LCD) panel having the pixel structure is also provided.

Abstract: A pixel structure suitable for being disposed on a substrate includes a thin film transistor (TFT), a first pixel electrode, a second pixel electrode, a scan line and a data line. The TFT disposed on the substrate includes a gate, a source, a first drain and a second drain. A main TFT is formed by the gate, the source and the first drain. A sub-thin film transistor (sub-TFT) is formed by the gate, the first drain and the second drain. The first pixel electrode is electrically connected to the first drain, and a portion of the first drain extends between the second pixel electrode and the substrate to form capacitor-coupling electrode. The second pixel electrode is electrically connected to the second drain of the sub-TFT. The scan line is disposed on the substrate and electrically connected to the gate, and the data line is electrically connected to the source.

Abstract: A pixel structure includes a gate, a source, a first drain, a second drain, a third drain, a first pixel electrode, a second pixel electrode, a scan line and a data line. The gate, the source and the first drain form a first thin film transistor. The gate, the source and the second drain form a second thin film transistor. The gate, the second drain and the third drain form a sub-thin film transistor (sub-TFT). Additionally, the first pixel electrode is electrically connected to the first drain, and the second drain extends to a portion between the second pixel electrode and the substrate such that a capacitor-coupling electrode is formed. Moreover, the second pixel electrode is electrically connected to the third drain of the sub-TFT. The scan line is disposed on the substrate and electrically connected to the gate, and the data line is electrically connected to the source.

Abstract: A pixel structure including a scan line, a data line, a first sub-pixel, a coupling electrode and a second sub-pixel is provided. The first sub-pixel includes a first thin film transistor (TFT) and a first pixel electrode, and the first pixel electrode is electrically connected to the scan line and the data line via the first TFT. The coupling electrode is disposed above the data line and electrically insulated from the data line. The second sub-pixel includes a second thin film transistor and a second pixel electrode. The second pixel electrode is electrically connected to the second TFT, and the second TFT is electrically connected to the coupling electrode. When seeing an image from a slant direction, color shift of image can be solved by utilizing the pixel structure. Besides, a liquid crystal display panel having the described pixel structure is also provided.

Abstract: A system for displaying images includes a thin film transistor array substrate including a substrate with thin film transistors array and at least one light-sensing element containing an amorphous silicon layer formed on the substrate, wherein the light-sensing element has a current flow direction perpendicular to the substrate.