Patents by Inventor Chih-Fu Chien
Chih-Fu Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7516058Abstract: IP characterization and for path finding methods, and a computer readable recording medium for storing program are provided. First, an Intellectual Property (IP) component is provided. Then, a plurality of test patterns for all paths in the IP component is automatically generated. The test patterns are then sequentially input into the IP component for simulation, and a plurality of corresponding simulation results is generated. Finally, an IP characteristic library is generated based on the simulation results.Type: GrantFiled: September 21, 2004Date of Patent: April 7, 2009Assignee: Faraday Technology Corp.Inventors: Peter Hanping Chen, Chih-Fu Chien, Jyh-Herng Wang, Hsu-Hui Tsai
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Patent number: 7389488Abstract: A method of finding a driving strength and a record medium accessible by a computer to store a program thereof are provided. The method is adapted to find the driving strength of an output pin of a target cell. Wherein, the driving strength of the output pin of the target cell is provided from the driving strength of a corresponding last level device. In this method, at least one candidate standard cell is searched in a standard cell library according to the last level device. Then, the driving strength of the target cell is interpolated between the driving strengths of the candidate standard cells to obtain the driving strength of the output pin of the target cell.Type: GrantFiled: May 25, 2005Date of Patent: June 17, 2008Assignee: Faraday Technology Corp.Inventors: Peter H. Chen, Chih-Fu Chien, Han-chi Liu, Jyh-Herng Wang
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Patent number: 7339225Abstract: A capacitor structure is provided. The capacitor structure is configured in a substrate. The capacitor structure includes a plurality of electrode sets, at least a first conductive plug and at least a second conductive plug. The electrode sets correspond with each other and are disposed in different layers of the substrate. Each electrode set comprises a first electrode and a second electrode surrounding the former. In addition, the first conductive plug and the second conductive plug are disposed between two adjacent electrode sets. First electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the first conductive plug. Similarly, second electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the second conductive plug.Type: GrantFiled: May 20, 2005Date of Patent: March 4, 2008Assignee: Faraday Technology Corp.Inventors: Chih-Fu Chien, Chao-Chi Lee, Cheng-Chung Chou
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Patent number: 7327551Abstract: A capacitor structure is provided. The capacitor structure is configured in a substrate. The capacitor structure includes a plurality of electrode sets, at least a first conductive plug and at least a second conductive plug. The electrode sets correspond with each other and are disposed in different layers of the substrate. Each electrode set includes a first electrode and a second electrode surrounding the former. In addition, the first conductive plug and the second conductive plug are disposed between two adjacent electrode sets. First electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the first conductive plug. Similarly, second electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the second conductive plug.Type: GrantFiled: November 19, 2006Date of Patent: February 5, 2008Assignee: Faraday Technology Corp.Inventors: Chih-Fu Chien, Chao-Chi Lee, Cheng-Chung Chou
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Publication number: 20070090429Abstract: A capacitor structure is provided. The capacitor structure is configured in a substrate. The capacitor structure includes a plurality of electrode sets, at least a first conductive plug and at least a second conductive plug. The electrode sets correspond with each other and are disposed in different layers of the substrate. Each electrode set comprises a first electrode and a second electrode surrounding the former. In addition, the first conductive plug and the second conductive plug are disposed between two adjacent electrode sets. First electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the first conductive plug. Similarly, second electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the second conductive plug.Type: ApplicationFiled: November 19, 2006Publication date: April 26, 2007Applicant: FARADAY TECHNOLOGY CORP.Inventors: Chih-Fu Chien, Chao-Chi Lee, Cheng-Chung Chou
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Publication number: 20060271889Abstract: A method of finding a driving strength and a record medium accessible by a computer to store a program thereof are provided. The method is adapted to find the driving strength of an output pin of a target cell. Wherein, the driving strength of the output pin of the target cell is provided from the driving strength of a corresponding last level device. In this method, at least one candidate standard cell is searched in a standard cell library according to the last level device. Then, the driving strength of the target cell is interpolated between the driving strengths of the candidate standard cells to obtain the driving strength of the output pin of the target cell.Type: ApplicationFiled: May 25, 2005Publication date: November 30, 2006Inventors: Peter H. Chen, Chih-Fu Chien, Han-chi Liu, Jyh-Herng Wang
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Publication number: 20060261439Abstract: A capacitor structure including a first electrode set and a second electrode set is provided. The first electrode set comprises a plurality of first stripe electrodes, which are parallel to each other, and a first coupling circuit. The first coupling circuit is coupled to a part of stripe electrodes, wherein the coupled first stripe electrodes and the uncoupled first stripe electrodes are alternately arranged. In addition, the second electrode set comprises a plurality of second stripe electrodes, which are parallel to each other, and a second coupling circuit. The second coupling circuit is coupled to a part of the second stripe electrodes, wherein the coupled second stripe electrodes and the uncoupled second stripe electrodes are alternately arranged. Furthermore, the coupled first stripe electrodes are coupled to the coupled second stripe electrodes, and the uncoupled first stripe electrodes are coupled to the uncoupled second stripe electrodes.Type: ApplicationFiled: May 17, 2005Publication date: November 23, 2006Inventors: Chih-Fu Chien, Chao-Chi Lee, Cheng-Chung Chou
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Publication number: 20060261394Abstract: A capacitor structure is provided. The capacitor structure is configured in a substrate. The capacitor structure includes a plurality of electrode sets, at least a first conductive plug and at least a second conductive plug. The electrode sets correspond with each other and are disposed in different layers of the substrate. Each electrode set comprises a first electrode and a second electrode surrounding the former. In addition, the first conductive plug and the second conductive plug are disposed between two adjacent electrode sets. First electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the first conductive plug. Similarly, second electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the second conductive plug.Type: ApplicationFiled: May 20, 2005Publication date: November 23, 2006Inventors: Chih-Fu Chien, Chao-Chi Lee, Cheng-Chung Chou
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Patent number: 7046055Abstract: A voltage detection circuit for detecting the voltage level of a first power source. A first transistor includes a first gate, a first source, and a first drain coupled to the first gate. A second transistor includes a second gate, a second source, and a second drain coupled to the second gate. A comparator includes a first input terminal, a second input terminal coupled to the second drain, and an output terminal. A first resistor is coupled between the first input terminal and the first drain. A second resistor is coupled to the first power source. A third resistor is coupled between the second resistor and the first input terminal. A fourth resistor is coupled between the second resistor and input terminal. A fifth resistor is coupled between the first source, and a second power source. A resistive device is coupled between the first source, and the first power source.Type: GrantFiled: October 14, 2005Date of Patent: May 16, 2006Assignee: Faraday Technology Corp.Inventors: Chao-Chi Lee, Yu-Tong Lin, Chih-Fu Chien
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Patent number: 7023244Abstract: A voltage detection circuit for detecting the voltage level of a first power source. A first transistor includes a first gate, a first source, and a first drain coupled to the first gate. A second transistor includes a second gate, a second source, and a second drain coupled to the second gate. A comparator includes a first input terminal, a second input terminal coupled to the second drain, and an output terminal. A first resistor is coupled between the first input terminal and the first drain. A second resistor is coupled to the first power source. A third resistor is coupled between the second resistor and the first input terminal. A fourth resistor is coupled between the second resistor and input terminal. A fifth resistor is coupled between the first source, and a second power source. A resistive device is coupled between the first source, and the first power source.Type: GrantFiled: June 24, 2004Date of Patent: April 4, 2006Assignee: Faraday Technology Corp.Inventors: Chao-Chi Lee, Yu-Tong Lin, Chih-Fu Chien
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Publication number: 20060062155Abstract: IP characterization and for path finding methods, and a computer readable recording medium for storing program are provided. First, an Intellectual Property (IP) component is provided. Then, a plurality of test patterns for all paths in the IP component is automatically generated. The test patterns are then sequentially input into the IP component for simulation, and a plurality of corresponding simulation results is generated. Finally, an IP characteristic library is generated based on the simulation results.Type: ApplicationFiled: September 21, 2004Publication date: March 23, 2006Inventors: Peter Hanping Chen, Chih-Fu Chien, Jyh-Herng Wang, Hsu-Hui Tsai
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Publication number: 20060033540Abstract: A voltage detection circuit for detecting the voltage level of a first power source. A first transistor includes a first gate, a first source, and a first drain coupled to the first gate. A second transistor includes a second gate, a second source, and a second drain coupled to the second gate. A comparator includes a first input terminal, a second input terminal coupled to the second drain, and an output terminal. A first resistor is coupled between the first input terminal and the first drain. A second resistor is coupled to the first power source. A third resistor is coupled between the second resistor and the first input terminal. A fourth resistor is coupled between the second resistor and input terminal. A fifth resistor is coupled between the first source, and a second power source. A resistive device is coupled between the first source, and the first power source.Type: ApplicationFiled: October 14, 2005Publication date: February 16, 2006Inventors: Chao-Chi Lee, Yu-Tong Lin, Chih-Fu Chien
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Publication number: 20050285635Abstract: A voltage detection circuit for detecting the voltage level of a first power source. A first transistor includes a first gate, a first source, and a first drain coupled to the first gate. A second transistor includes a second gate, a second source, and a second drain coupled to the second gate. A comparator includes a first input terminal, a second input terminal coupled to the second drain, and an output terminal. A first resistor is coupled between the first input terminal and the first drain. A second resistor is coupled to the first power source. A third resistor is coupled between the second resistor and the first input terminal. A fourth resistor is coupled between the second resistor and input terminal. A fifth resistor is coupled between the first source, and a second power source. A resistive device is coupled between the first source, and the first power source.Type: ApplicationFiled: June 24, 2004Publication date: December 29, 2005Inventors: Chao-Chi Lee, Yu-Tong Lin, Chih-Fu Chien
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Patent number: 6538868Abstract: An electrostatic discharge protective circuit can receive a pre-stage driver output and involve a first PMOS transistor, a first NMOS transistor and a second NMOS transistor and all connect in series. More particularly, a source region of the first PMOS transistor connects to a system power source; and a drain region connects to a conductive pad, and a gate receives the pre-stage driver output. A gate of the first NMOS transistor connects to a first node A, a gate of the second NMOS transistor connects to a third node C and a source region connects to a grounded node. The third node C also can receive the pre-stage driver output. There is a first resistor between the first node A and the system power source. There is a second PMOS transistor in between the first node A and the third node C and connect with two source/drain regions. And the substrate of the second PMOS transistor also connects with the first node A. Also, a gate of the second PMOS transistor connects with a second node B.Type: GrantFiled: September 6, 2002Date of Patent: March 25, 2003Assignee: Faraday Technology Corp.Inventors: Hung-Yi Chang, Yi-Hua Chang, Chih-Fu Chien
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Publication number: 20030007298Abstract: An electrostatic discharge protective circuit can receive a pre-stage driver output and involve a first PMOS transistor, a first NMOS transistor and a second NMOS transistor and all connect in series. More particularly, a source region of the first PMOS transistor connects to a system power source; and a drain region connects to a conductive pad, and a gate receives the pre-stage driver output. A gate of the first NMOS transistor connects to a first node A, a gate of the second NMOS transistor connects to a third node C and a source region connects to a grounded node. The third node C also can receive the pre-stage driver output. There is a first resistor between the first node A and the system power source. There is a second PMOS transistor in between the first node A and the third node C and connect with two source/drain regions. And the substrate of the second PMOS transistor also connects with the first node A. Also, a gate of the second PMOS transistor connects with a second node B.Type: ApplicationFiled: September 6, 2002Publication date: January 9, 2003Inventors: Hung-Yi Chang, Yi-Hua Chang, Chih-Fu Chien
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Patent number: 6469560Abstract: An electrostatic discharge protective circuit can receive a pre-stage driver output and involve a first PMOS transistor, a first NMOS transistor and a second NMOS transistor and all connect in series. More particularly, a source region of the first PMOS transistor connects to a system power source; and a drain region connects to a conductive pad, and a gate receives the pre-stage driver output. A gate of the first NMOS transistor connects to a first node A, a gate of the second NMOS transistor connects to a third node C and a source region connects to a grounded node. The third node C also can receive the pre-stage driver output. There is a first resistor between the first node A and the system power source. There is a second PMOS transistor in between the first node A and the third node C and connect with two source/drain regions. And the substrate of the second PMOS transistor also connects with the first node A. Also, a gate of the second PMOS transistor connects with a second node B.Type: GrantFiled: June 28, 2001Date of Patent: October 22, 2002Assignee: Faraday Technology Corp.Inventors: Hung-Yi Chang, Yi-Hua Chang, Chih-Fu Chien
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Patent number: 6456115Abstract: A clock gate buffering circuit is having a functional circuit without a latch that receives a clock and an enable signal. A logic voltage of an enable signal sends a corresponding clock gate signal to provide the other circuit when the clock of the functional circuit is in a rising edge. Also, the logical voltage of the enable signal sends a corresponding clock gate signal to provide the other circuit when this functional circuit is also in falling edge.Type: GrantFiled: February 8, 2001Date of Patent: September 24, 2002Assignee: Faraday Technology Corp.Inventors: Guo-Wei Li, Jeng-Huang Wu, Chih-Fu Chien
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Publication number: 20010013796Abstract: A clock gate buffering circuit is having a functional circuit without a latch that receives a clock and an enable signal. A logic voltage of an enable signal sends a corresponding clock gate signal to provide the other circuit when the clock of the functional circuit is in a rising edge. Also, the logical voltage of the enable signal sends a corresponding clock gate signal to provide the other circuit when this functional circuit is also in falling edge.Type: ApplicationFiled: February 8, 2001Publication date: August 16, 2001Inventors: Guo-Wei Li, Jeng-Huang Wu, Chih-Fu Chien