Patents by Inventor Chih-Han Lin

Chih-Han Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11522084
    Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: December 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 11522073
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: December 6, 2022
    Assignee: TAIWAN SEMICONDUTOR MANUFACTURING COMPANY LIMITED
    Inventors: Shih-Yao Lin, Chih-Han Lin, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee
  • Patent number: 11517246
    Abstract: Disclosed herein is a method for diagnosing a neurological disorder based on at least one magnetic resonance imaging (MRI) image. The method includes identifying brain image regions that contain a respective portion of diffusion index values of at least one diffusion index. For each of the brain image regions, a characteristic parameter based on the respective portion of the diffusion index values is calculated. a diagnoses is then made for the brain using one of predetermined categories of the neurological disorder by performing classification on a combination of the characteristic parameters via a classifier.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: December 6, 2022
    Assignees: Chang Gung Memorial Hospital, Linkou, Chang GungUniversitv, Change Gung Medical Foundation Chang Gung Memorial Hospital at Keelung
    Inventors: Jiun-Jie Wang, Yi-Hsin Weng, Shu-Hang Ng, Jur-Shan Cheng, Yi-Ming Wu, Yao-Liang Chen, Wey-Yil Lin, Chin-Song Lu, Wen-Chuin Hsu, Chia-Ling Chen, Yi-Chun Chen, Sung-Han Lin, Chih-Chien Tsai
  • Publication number: 20220382143
    Abstract: A method is provided. The method includes detaching an upper shell of a reticle pod from a base. The method further includes while the upper shell is detached from the base, blocking an inlet flow of gas from entering an interior of the reticle pod between the upper shell and the base with a use of a fluid regulating module which is in a sealed state. In the sealed state of the fluid regulating module, an opening of the fluid regulating module is covered with a sealing film. The method also includes removing a reticle positioned on the base to a process tool. In addition, the method includes performing a lithography operation in the process tool with the use of the reticle.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: TZU HAN LIU, CHIH-WEI WEN, CHUNG-HUNG LIN
  • Publication number: 20220384263
    Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
  • Publication number: 20220384617
    Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Chen-Ping Chen, Kuei-Yu Kao, Shih-Yao Lin, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20220384348
    Abstract: A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Chih-Yu Chang, Meng-Han Lin, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin
  • Publication number: 20220384239
    Abstract: A wafer fabricating system includes a wafer chuck, a gas inlet port, a fluid inlet port, first and second arc-shaped channels, a gas source, and a fluid containing source. The wafer chuck has a top surface, and orifices are formed on the top surface. The gas inlet port is formed in the wafer chuck and located underneath a fan-shaped sector of the top surface, wherein the gas inlet port is fluidly communicated with the orifices. The fluid inlet port is formed in the wafer chuck. The first and second arc-shaped channels are fluidly communicated with the fluid inlet port and located underneath the fan-shaped sector of the top surface and located at opposite sides of the gas inlet port from a top view. The gas source fluidly is connected to the gas inlet port. The fluid containing source fluidly is connected to the fluid inlet port.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 1, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chun YANG, Yi-Ming LIN, Po-Wei LIANG, Chu-Han HSIEH, Chih-Lung CHENG, Po-Chih HUANG
  • Patent number: 11515422
    Abstract: A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate. The gate stack has a conductive structure and a gate dielectric layer, and a top of the gate dielectric layer is higher than a top of the conductive structure. The semiconductor device also includes a protection element over the gate stack. The semiconductor device further includes a spacer extending along a side surface of the protection element and a sidewall of the gate stack.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: November 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Publication number: 20220376071
    Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.
    Type: Application
    Filed: July 8, 2021
    Publication date: November 24, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Tsai, Jung Han, Ming-Chi Li, Chih-Mou Lin, Yu-Hsiang Hung, Yu-Hsiang Lin, Tzu-Lang Shih
  • Patent number: 11508825
    Abstract: A Fin FET semiconductor device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The Fin FET device also includes a gate stack including a gate electrode layer, a gate dielectric layer, side wall insulating layers disposed at both sides of the gate electrode layer, and interlayer dielectric layers disposed at both sides of the side wall insulating layers. The gate stack is disposed over the isolation insulating layer, covers a portion of the fin structure, and extends in a second direction perpendicular to the first direction. A recess is formed in an upper surface of the isolation insulating layer not covered by the side wall insulating layers and the interlayer dielectric layers. At least part of the gate electrode layer and the gate dielectric layer fill the recess.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 11508849
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Cheng Chang, Kai-Yu Cheng, Chih-Han Lin, Sin-Yi Yang, Horng-Huei Tseng
  • Patent number: 11508719
    Abstract: An ESD circuit is connected between an I/O pad and a first node. The ESD circuit includes a bi-directional buck circuit, a triggering circuit and a discharging circuit. The bi-directional buck circuit includes a forward path and a reverse path. The forward path and the reverse path are connected between the I/O pad and a second node. The triggering circuit is connected between the second node and the first node. The discharging circuit is connected between the second node and the first node, and connected with the triggering circuit. When the I/O pad receives negative ESD zap, the ESD current flows from the first node to the I/O pad through the discharging circuit and the reverse path. When the I/O pad receives positive ESD zap, the ESD current flows from the I/O pad to the first node through the forward path and the discharging circuit.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: November 22, 2022
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Yun-Jen Ting, Chih-Wei Lai, Yi-Han Wu, Kun-Hsin Lin, Hsin-Kun Hsu
  • Publication number: 20220367464
    Abstract: An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate. The n-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle. The p-type semiconductor device is present on the substrate. The p-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Inventors: Che-Cheng CHANG, Chih-Han LIN, Horng-Huei TSENG
  • Publication number: 20220367701
    Abstract: Methods for manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate a substrate and channel layers vertically stacked over the substrate. The semiconductor structure also includes a dielectric fin structure formed adjacent to the channel layers and a gate structure abutting the channel layers and the dielectric fin structure. The semiconductor structure also includes a source/drain structure attached to the channel layers and a contact formed over the source/drain structure. The semiconductor structure also includes a Si layer covering a portion of a top surface of the source/drain structure. In addition, the Si layer is sandwiched between the dielectric fin structure and the contact.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Chen-Han WANG, Pei-Hsun WANG, Chun-Hsiung LIN, Chih-Hao WANG
  • Publication number: 20220367672
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao LIN, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee, Chih-Han Lin
  • Publication number: 20220367719
    Abstract: A device includes a substrate, a shallow trench isolation (STI) structure, an isolation structure, and a gate stack. The substrate has a semiconductor fin. The shallow trench isolation (STI) structure is over the substrate and laterally surrounding the semiconductor fin. The isolation structure is disposed on a top surface of the STI structure. The gate stack crosses the semiconductor fin, over the STI structure, and in contact with a sidewall the isolation structure, in which the gate stack includes a high-k dielectric layer extending from a sidewall of the semiconductor fin to the top surface of the STI structure and terminating prior to reaching the sidewall of the isolation structure, and the high-k dielectric layer is in contact with the top surface of the STI structure. The gate stack includes a gate electrode over the high-k dielectric layer and in contact with the sidewall of the isolation structure.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng CHANG, Chih-Han LIN
  • Publication number: 20220359709
    Abstract: A method includes forming a dummy gate electrode on a semiconductor region, forming a first gate spacer on a sidewall of the dummy gate electrode, and removing an upper portion of the first gate spacer to form a recess, wherein a lower portion of the first gate spacer remains, filling the recess with a second gate spacer, removing the dummy gate electrode to form a trench, and forming a replacement gate electrode in the trench.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20220359722
    Abstract: A method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second dummy gate dielectric of the second dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
  • Patent number: D969485
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: November 15, 2022
    Assignee: GUDENG PRECISION INDUSTRIAL CO., LTD.
    Inventors: Ming-Chien Chiu, Chih-Ming Lin, Po-Ting Lee, Cheng-En Chung, Nien-Yun Yu, Yi-Duang Huang, Cheng-Han Chou