Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

Abstract: A semiconductor device and method for fabricating a semiconductor device includes etch selectivity tuning to enlarge epitaxy process windows. Through modification of etching processes and careful selection of materials, improvements in semiconductor device yield and performance can be delivered. Etch selectivity is controlled by using dilute gas, using assistive etch chemicals, controlling a magnitude of bias power used in the etching process, and controlling an amount of passivation gas used in the etching process, among other approaches. A recess is formed in a dummy fin in a region of the semiconductor where epitaxial growth occurs to further enlarge the epitaxy process window.

Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.

Abstract: A cyclic process including an etching process, a passivation process, and a pumping out process is provided to prevent over etching of the sacrificial gate electrode, particularly when near a high-k dielectric feature. The cyclic process solves the problems of failed gate electrode layer at an end of channel region and enlarges filling windows for replacement gate structures, thus improving channel control. Compared to state-of-art solutions, embodiments of the present disclosure also enlarge volume of source/drain regions, thus improving device performance.

Abstract: A semiconductor device includes at least one semiconductor fin, a gate electrode, at least one gate spacer, and a gate dielectric. The semiconductor fin includes at least one recessed portion and at least one channel portion. The gate electrode is present on at least the channel portion of the semiconductor fin. The gate spacer is present on at least one sidewall of the gate electrode. The gate dielectric is present at least between the channel portion of the semiconductor fin and the gate electrode. The gate dielectric extends farther than at least one end surface of the channel portion of the semiconductor fin.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface, and an etch stop layer extends between the portion of the bottom surface of the gate spacer and the top surface of the topmost semiconductor layer.

Abstract: A method of fabricating a semiconductor structure includes forming a recess in an active channel structure by removing a portion thereof, filling the recess with a dielectric material, forming a cladding layer adjacent the active channel structure but not adjacent the dielectric material, and forming a gate structure comprising a first gate structure and a second gate structure around the active channel structure. A width of the dielectric material in the recess is greater than a width of the first gate structure and a width of the second gate structure.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: A semiconductor device includes a semiconductor fin extending from a substrate, and a gate structure extending across the semiconductor fin. From a plan view, the semiconductor fin includes a first sidewall, a second sidewall opposing the first sidewall, an end surface extending along a different direction than the first sidewall and the second sidewall, and a first corner portion connecting the first sidewall and the end surface. The first corner portion is more rounded than the first sidewall and the end surface.

Abstract: A method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second dummy gate dielectric of the second dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.

Abstract: Semiconductor devices and methods for forming the semiconductor devices using a cap layer are provided. The semiconductor devices include a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers, and a gate spacer that extends along a sidewall of the upper portion of the gate structure. In some examples, a gap dimension measured between the gate spacer and an adjacent one of the plurality of semiconductor layers is sufficiently small such that the gate structure does not contact the source/drain structures. In some examples, the gate spacer and an adjacent one of the one or more semiconductor layers of the fin structure are separated by a cap layer.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.

Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

Abstract: A semiconductor fabrication method includes: forming an epitaxial stack including at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a plurality of fins in the epitaxial stack; performing tuning operations to prevent a width of the sacrificial epitaxial layer expanding beyond a width of the channel epitaxial layer during operations to form isolation features; forming the isolation features between the plurality of fins, wherein the width of the sacrificial epitaxial layer does not expand beyond the width of the channel epitaxial layer; forming a sacrificial gate stack; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; forming inner spacers around the sacrificial epitaxial layer and the channel epitaxial layer; forming source/drain features; removing the sacrificial gate stack and sacrificial epitaxial layer; and forming a replacement metal gate, wherein the metal gate is shielded from the source/drain features.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.