Abstract: An electronic paper device includes a touch cover plate module, a front lighting module and an electronic paper display module. The touch cover plate module has a top plate, a touch sensor and a bottom plate. The top plate is disposed with a black bezel. The bottom plate is disposed with a transparent conductive film with a low refractive index. The front lighting module has a light guide plate. An outer edge portion of the light guide plate is disposed with a point light source. The point light source emits light from a side of the light guide plate to convert the emitted light into a surface light source. An upper surface of the light guide plate is attached on the transparent conductive film to form a total reflection interface on the light guide plate and an electromagnetic mask layer between the touch sensor and the electronic paper display module.

Abstract: A semiconductor device may be formed by forming a first fin and a second fin in a first area and a second area of a substrate, respectively; which may be followed by forming of a first dummy gate structure and a second dummy gate structure straddling the first fin and second fin, respectively and forming a sacrificial layer extending along a bottom portion of the second dummy gate structure. The first dummy gate structure may be replaced with a first metal gate structure, while the second dummy gate structure and the sacrificial layer may be replaced with a second metal gate structure.

Abstract: A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.

Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.

Abstract: A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a conformal capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer is disposed along sidewalls of the first trench and forming a conductive feature within the first trench and the second trench.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion. The lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and comprises a first layer and a second layer. The first layer is in contact with a first portion of the sidewall and the second layer is in contact with a second portion of the sidewall.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction. The gate structure includes a first portion and a second portion separated by the gate isolation structure and the dielectric fin. The first portion of the gate structure presents a first beak profile and the second portion of the gate structure presents a second beak profile. The first and second beak profiles point toward each other.

Abstract: A semiconductor device includes an isolation insulating layer disposed over a substrate, a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer, a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer, gate sidewall spacers disposed over opposing side faces of the gate structure, and a source/drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin. The first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.

Abstract: A semiconductor device includes a fin extending from a substrate, a gate stack over and along a sidewall of the fin, a spacer along a first sidewall of the gate stack and the sidewall of the fin, a dummy gate material along the sidewall of the fin, wherein the dummy gate material is between the spacer and the gate stack, and a first epitaxial source/drain region in the fin and adjacent the gate stack.

Abstract: A method includes forming a first protruding semiconductor fin and a dummy fin protruding higher than top surfaces of isolation regions. The first protruding semiconductor fin is parallel to the dummy fin, forming a gate stack on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin. The method further includes recessing a third portion of the first protruding semiconductor fin to form a recess, recessing an fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin, and forming an epitaxy semiconductor region in the recess. The epitaxy semiconductor region is grown toward the dummy fin.

Abstract: A device includes a semiconductor fin semiconductor fin extending from a substrate, a gate structure extending across the semiconductor fin, and a multilayer gate spacer on a sidewall of the gate structure. The multilayer gate spacer includes an inner spacer layer, an outer spacer layer, and a dielectric structure. The inner spacer layer has a vertical portion extending along the sidewall of the gate structure, and a lateral portion laterally extending from the vertical portion in a direction away from the gate structure. The outer spacer layer is spaced apart from the vertical portion of the inner spacer layer by an air gap. The dielectric structure spaces apart a bottom end of the outer spacer layer from the lateral portion of the inner spacer layer.

Abstract: A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal

Abstract: A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.

Abstract: An interconnect structure is provided. The interconnect structure includes a transistor on a substrate, a first dielectric layer over the transistor, a first metal line through the first dielectric layer, a second dielectric layer over the first dielectric layer, and a via through the second dielectric layer and on the first metal line. A first side surface of the first dielectric layer includes a first portion in direct contact with the first metal line and a second portion in direct contact with the via, and the first portion of the first side surface of the first dielectric layer is aligned with the second portion of the first side surface of the first dielectric layer.

Abstract: A semiconductor device includes an isolation insulating layer disposed over a substrate, a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer, a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer, gate sidewall spacers disposed over opposing side faces of the gate structure, and a source/drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin. The first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.

Abstract: A semiconductor device includes a first stack structure, a second stack structure, and a third stack structure. Each of the stack structure includes semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction and wraps around each of the semiconductor layers. The semiconductor layers of the first stack structure are coupled with respective source/drain structures. The semiconductor layers of the second stack structure are coupled with respective source/drain structures. The semiconductor layers of the third stack structure are coupled with a dielectric passivation layer.

Abstract: A device comprises a first metal structure, a dielectric structure, a dielectric residue, and a second metal structure. The dielectric structure is over the first metal structure. The dielectric structure has a stepped sidewall structure. The stepped sidewall structure comprises a lower sidewall and an upper sidewall laterally set back from the lower sidewall. The dielectric residue is embedded in a recessed region in the lower sidewall of the stepped sidewall structure of the dielectric structure. The second metal structure extends through the dielectric structure to the first metal structure.