Patents by Inventor Chih-Han Lin

Chih-Han Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200365471
    Abstract: Bridging testing method between adjacent semiconductor devices includes forming patterned diffusion region on semiconductor substrate, and forming first conductive layer over diffusion region. First conductive layer is patterned in same pattern as patterned diffusion region. Second conductive layer formed extending in first direction over first conductive layer. Second conductive layer is patterned to form opening extending in first direction in central region of second conductive layer exposing portion of first conductive layer. First conductive layer exposed portion is removed exposing portion of diffusion region. Source/drain region is formed over exposed portion of diffusion region, and dielectric layer is formed over source/drain region. Third conductive layer is formed over dielectric layer. End portions along first direction of second conductive layer removed to expose first and second end portions of first conductive layer.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Meng-Han LIN, Chia-Lin LIANG, Chih-Ren HSIEH
  • Publication number: 20200365578
    Abstract: An ESD circuit is connected between an I/O pad and a first node. The ESD circuit includes a bi-directional buck circuit, a triggering circuit and a discharging circuit. The bi-directional buck circuit includes a forward path and a reverse path. The forward path and the reverse path are connected between the I/O pad and a second node. The triggering circuit is connected between the second node and the first node. The discharging circuit is connected between the second node and the first node, and connected with the triggering circuit. When the I/O pad receives negative ESD zap, the ESD current flows from the first node to the I/O pad through the discharging circuit and the reverse path. When the I/O pad receives positive ESD zap, the ESD current flows from the I/O pad to the first node through the forward path and the discharging circuit.
    Type: Application
    Filed: March 4, 2020
    Publication date: November 19, 2020
    Inventors: Yun-Jen TING, Chih-Wei LAI, Yi-Han WU, Kun-Hsin LIN, Hsin-Kun HSU
  • Patent number: 10840379
    Abstract: A device includes a semiconductive fin, a first gate stack, a second gate stack, an insulating structure, and a spacer. The semiconductive fin extends along a first direction. The first gate stack extends along a second direction and across the semiconductive fin. The first gate stack includes a high-? dielectric layer and a gate electrode. The high-? dielectric layer is over the semiconductive fin. The gate electrode is over the high-? dielectric layer. The second gate stack extends along the second direction and is substantially aligned with the first gate stack along the second direction. The insulating structure is between the first gate stack and the second gate stack. The high-? dielectric layer is spaced apart from the insulating structure. The spacer extends along a sidewall of the first gate stack and beyond a first sidewall of the insulating structure that faces the first gate stack.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10840144
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10840153
    Abstract: A method includes providing a structure having a first region and a second region, the first region including a first channel region, the second region including a second channel region; forming a gate stack layer over the first and second regions; patterning the gate stack layer, thereby forming a first gate stack over the first channel region and a second gate stack over the second channel region; and laterally etching bottom portions of the first and second gate stacks by applying different etchant concentrations to the first and second regions simultaneously, thereby forming notches at the bottom portions of the first and second gate stacks.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10840242
    Abstract: A method includes, in a first etching step, etching a semiconductor substrate to form first recesses in a first device region and second recesses in a second device regions simultaneously. A first semiconductor strip is formed between the first recesses. A second semiconductor strip is formed between the second recesses. In a second etching step, the semiconductor substrate in the second device region is etched to extend the second recesses. The first recesses and the second recesses are filled with a dielectric material to form first and second isolation regions in the first and second recesses, respectively. The first isolation regions and the second isolation regions are recessed. Portions of the semiconductor substrate in the first and the second device regions protrude higher than top surfaces of the respective first and second isolation regions to form a first and a second semiconductor fin, respectively.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Publication number: 20200343355
    Abstract: A Fin FET semiconductor device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The Fin FET device also includes a gate stack including a gate electrode layer, a gate dielectric layer, side wall insulating layers disposed at both sides of the gate electrode layer, and interlayer dielectric layers disposed at both sides of the side wall insulating layers. The gate stack is disposed over the isolation insulating layer, covers a portion of the fin structure, and extends in a second direction perpendicular to the first direction. A recess is formed in an upper surface of the isolation insulating layer not covered by the side wall insulating layers and the interlayer dielectric layers. At least part of the gate electrode layer and the gate dielectric layer fill the recess.
    Type: Application
    Filed: July 13, 2020
    Publication date: October 29, 2020
    Inventors: Che-Cheng CHANG, Chih-Han LIN
  • Publication number: 20200335499
    Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and source and drain regions is described. The substrate has a plurality of fins and a plurality of insulators disposed between the fins. The source and drain regions are disposed on two opposite sides of the at least one gate structure. The gate structure is disposed over the plurality of fins and disposed on the plurality of insulators. The gate structure includes a stacked strip disposed on the substrate and a gate electrode stack disposed on the stacked strip. The spacers are disposed on opposite sidewalls of the gate structure, and the gate electrode stack contacts sidewalls of the opposite spacers.
    Type: Application
    Filed: July 1, 2020
    Publication date: October 22, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10811578
    Abstract: A LED carrier includes a substrate, a conductive layer, an adhesive layer, and a reflector. The conductive layer is disposed on the substrate, and has a bonding portion and an extending portion. The bonding portion has a top surface higher than a top surface of the extending portion. The adhesive layer covers the extending portion of the conductive layer and exposes the bonding portion of the conductive layer. The reflector is disposed over the adhesive layer. The adhesive layer has a hook portion in contact with a corner of the reflector.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: October 20, 2020
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Chih-Hao Lin, Chun-Peng Lin, Chang-Han Chen, Kuang-Neng Yang, Cheng-Ta Kuo
  • Patent number: 10811536
    Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10811506
    Abstract: A method includes receiving a device having a substrate and a first dielectric layer surrounding a gate trench. The method further includes depositing a gate dielectric layer and a gate work function (WF) layer in the gate trench and forming a hard mask (HM) layer in a space in the gate trench and surrounded by the gate WF layer. The method further includes recessing the gate WF layer such that a top surface of the gate WF layer in the gate trench is below a top surface of the first dielectric layer. After the recessing of the gate WF layer, the method further includes removing the HM layer in the gate trench and depositing a metal layer in the gate trench. The metal layer is in physical contact with a sidewall surface of the gate WF layer that is deposited before the HM layer is formed.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD.
    Inventors: Chih-Han Lin, Che-Cheng Chang, Horng-Huei Tseng
  • Patent number: 10811538
    Abstract: A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate. The gate stack has a work function layer and a gate dielectric layer, and tops of the work function layer and the gate dielectric layer are at different height levels. The semiconductor device also includes a protection element over the gate stack. The semiconductor device further includes a spacer extending along a side surface of the protection element and a sidewall of the gate stack.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10811412
    Abstract: A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first portion in contact with and embedded in the first concave. The drain includes a second portion in contact with and embedded in the second concave. The first portion and the second portion are covered by the gate stack.
    Type: Grant
    Filed: July 28, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Publication number: 20200328286
    Abstract: A method of forming a semiconductor structure includes forming a dummy gate feature over a semiconductive fin; forming a first spacer around the dummy gate feature and a second spacer around the first spacer; replacing the dummy gate feature with a metal gate feature; after replacing the dummy gate feature with the metal gate feature, partially removing the second spacer such that a top of the second spacer is lower than a top of the first spacer; and depositing a capping layer over and in contact with the metal gate feature and the first spacer.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin CHEN, Che-Cheng CHANG, Chih-Han LIN
  • Publication number: 20200328308
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: Che-Cheng Chang, Kai-Yu Cheng, Chih-Han Lin, Sin-Yi Yang, Horng-Huei Tseng
  • Patent number: 10804281
    Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu, Chih-Pin Huang
  • Publication number: 20200321196
    Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin CHEN, Tung-Wen CHENG, Che-Cheng CHANG, Jr-Jung LIN, Chih-Han LIN
  • Patent number: 10796955
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first metal layer formed over a substrate and a dielectric layer formed over the first metal layer. The semiconductor device structure further includes an adhesion layer formed in the dielectric layer and over the first metal layer and a second metal layer formed in the dielectric layer. The second metal layer is electrically connected to the first metal layer, and a portion of the adhesion layer is formed between the second metal layer and the dielectric layer. The adhesion layer includes a first portion lining with a top portion of the second metal layer, and the first portion has an extending portion along a vertical direction.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10797140
    Abstract: A semiconductor device and method of manufacture are provided. A source/drain region is formed next to a spacer, which is adjacent to a gate electrode. An implantation is performed through an implantation mask into the source/drain region as well as the first spacer, forming an implantation region within the spacer.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Publication number: 20200310243
    Abstract: The present disclosure provides a photomask, including a front side having a patterned layer, a back side opposite to the front side, a sidewall connecting the front side and the back side, a reflective layer between the front side and the back side, and a polymer layer on the backside of the photomask.
    Type: Application
    Filed: February 19, 2020
    Publication date: October 1, 2020
    Inventors: TZU HAN LIU, CHIH-WEI WEN, CHUNG-HUNG LIN