Abstract: A power voltage supply device, including a reference bias voltage generating circuit, a temperature compensation bias voltage generating circuit, a compensation voltage generator, and a voltage buffer, is provided. The reference bias voltage generating circuit generates a reference bias voltage. The temperature compensation bias voltage generating circuit generates a temperature compensation bias voltage that changes as temperature rises. The compensation voltage generator generates a first power voltage based on the reference bias voltage, and selectively boosts the first power voltage based on the temperature compensation bias voltage. An input terminal of the voltage buffer receives the first power voltage. The voltage buffer generates a second power voltage corresponding to the first power voltage to a load circuit.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first substrate including a first face and a second face opposite the first face. A second substrate is bonded to the first face of the first substrate such that the second face of the first substrate faces away from the second substrate. One or more recesses are arranged in the second face of the first substrate and are configured to compensate for thermal expansion or thermal contraction.

Abstract: An anti-fuse sensing device and an operation method thereof are provided. The anti-fuse sensing device includes an anti-fuse sensing circuit, a voltage generating circuit, and a power-on detection circuit. During a power-on transient period of the voltage generating circuit, the power-on detection circuit provides an initialization voltage to a control terminal of the anti-fuse sensing circuit to prevent a voltage level of the control terminal of the anti-fuse sensing circuit from being in an unknown state. After the power-on transient period ends, the voltage generating circuit provides a control voltage to the control terminal of the anti-fuse sensing circuit. The anti-fuse sensing circuit senses a resistance state of an anti-fuse based on the control voltage. During the period when the voltage generating circuit provides the control voltage, the power-on detection circuit stops providing the initialization voltage to the control terminal of the anti-fuse sensing circuit.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first substrate including a first face and a second face opposite the first face. A second substrate is bonded to the first face of the first substrate such that the second face of the first substrate faces away from the second substrate. One or more recesses are arranged in the second face of the first substrate and are configured to compensate for thermal expansion or thermal contraction.

Abstract: An anti-fuse sensing device and an operation method thereof are provided. The anti-fuse sensing device is adapted for sensing a resistance state of an anti-fuse. The anti-fuse sensing device includes a voltage generating circuit, a comparison circuit, and a sensing circuit. The voltage generating circuit is configured to generate a comparison voltage that changes with temperature. The comparison circuit is coupled to the voltage generating circuit to receive the comparison voltage. The comparison circuit is configured to compare the comparison voltage with a reference voltage, and convert a difference between the comparison voltage and the reference voltage into a bias voltage that changes with temperature. The sensing circuit is coupled to the comparison circuit to receive the bias voltage. The sensing circuit is configured to sense the resistance state of the anti-fuse according to the bias voltage.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first substrate including a first face and a second face opposite the first face. A second substrate is bonded to the first face of the first substrate such that the second face of the first substrate faces away from the second substrate. One or more recesses are arranged in the second face of the first substrate and are configured to compensate for thermal expansion or thermal contraction.

Abstract: In an embodiment, a system includes: a circular frame comprising a first side and a second side opposite the first side, wherein the circular frame comprises an aperture formed therethrough; an insert disposed within the aperture; a first wafer disposed over the insert; a second wafer disposed over the first wafer, wherein both the first wafer and the second wafer are configured for eutectic bonding when heated; two clamps disposed on the first side along the circular frame, wherein the two clamps are configured to contact the second wafer at respective clamp locations; and a plurality of pieces configured to secure the insert within the aperture, the plurality of pieces comprising both fixed and flexible pieces, the plurality of pieces comprising two fixed pieces disposed respectively adjacent to the clamp locations along the second side of the circular frame.

Abstract: A microelectromechanical systems (MEMS) package with roughness for high quality anti-stiction is provided. A device substrate is arranged over a support device. The device substrate comprises a movable element with a lower surface that is rough and that is arranged within a cavity. A dielectric layer is arranged between the support device and the device substrate. The dielectric layer laterally encloses the cavity. An anti-stiction layer lines the lower surface of the movable element. A method for manufacturing the MEMS package is also provided.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first wafer comprising a first face and a second face opposite the first face and having a plurality of predetermined die areas. A plurality of recesses are disposed in the first face of the first wafer. A first recess of the plurality of recesses extends in a direction substantially parallel to a first edge of at least one of the plurality of predetermined die areas and laterally surrounds the at least one of the plurality of predetermined die areas. A second wafer is bonded to the second face of the first wafer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first wafer comprising a first face and a second face opposite the first face and having a plurality of predetermined die areas. A plurality of recesses are disposed in the first face of the first wafer. A first recess of the plurality of recesses extends in a direction substantially parallel to a first edge of at least one of the plurality of predetermined die areas and laterally surrounds the at least one of the plurality of predetermined die areas. A second wafer is bonded to the second face of the first wafer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes receiving a first wafer having multiple predetermined die areas. The method also includes forming a recess in the first wafer, and the recess extends in a direction substantially parallel to an edge of one of the predetermined die areas. The method further includes receiving a second wafer. In addition, the method includes bonding the first wafer and the second wafer at an elevated temperature after the recess is formed.

Abstract: A microelectromechanical systems (MEMS) package with roughness for high quality anti-stiction is provided. A device substrate is arranged over a support device. The device substrate comprises a movable element with a lower surface that is rough and that is arranged within a cavity. A dielectric layer is arranged between the support device and the device substrate. The dielectric layer laterally encloses the cavity. An anti-stiction layer lines the lower surface of the movable element. A method for manufacturing the MEMS package is also provided.

Abstract: In an embodiment, a system includes: a circular frame comprising a first side and a second side opposite the first side, wherein the circular frame comprises an aperture formed therethrough; an insert disposed within the aperture; a first wafer disposed over the insert; a second wafer disposed over the first wafer, wherein both the first wafer and the second wafer are configured for eutectic bonding when heated; two clamps disposed on the first side along the circular frame, wherein the two clamps are configured to contact the second wafer at respective clamp locations; and a plurality of pieces configured to secure the insert within the aperture, the plurality of pieces comprising both fixed and flexible pieces, the plurality of pieces comprising two fixed pieces disposed respectively adjacent to the clamp locations along the second side of the circular frame.

Abstract: A method for forming a semiconductor device structure is provided. The method includes receiving a first wafer having multiple predetermined die areas. The method also includes forming a recess in the first wafer, and the recess extends in a direction substantially parallel to an edge of one of the predetermined die areas. The method further includes receiving a second wafer. In addition, the method includes bonding the first wafer and the second wafer at an elevated temperature after the recess is formed.

Abstract: A microelectromechanical systems (MEMS) package with roughness for high quality anti-stiction is provided. A device substrate is arranged over a support device. The device substrate comprises a movable element with a lower surface that is rough and that is arranged within a cavity. A dielectric layer is arranged between the support device and the device substrate. The dielectric layer laterally encloses the cavity. An anti-stiction layer lines the lower surface of the movable element. A method for manufacturing the MEMS package is also provided.

Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a recess in a first substrate and forming a dielectric layer on the first substrate and in the recess. The method also includes forming a second substrate on the dielectric layer and etching a portion of the second substrate to form a MEMS structure. The MEMS structure has a plurality of openings. The method further includes etching a portion of the dielectric layer to form a cavity below the openings.

Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a recess in a first substrate and forming a dielectric layer on the first substrate and in the recess. The method also includes forming a second substrate on the dielectric layer and etching a portion of the second substrate to form a MEMS structure. The MEMS structure has a plurality of openings. The method further includes etching a portion of the dielectric layer to form a cavity below the openings.

Abstract: A microelectromechanical systems (MEMS) package with roughness for high quality anti-stiction is provided. A device substrate is arranged over a support device. The device substrate comprises a movable element with a lower surface that is rough and that is arranged within a cavity. A dielectric layer is arranged between the support device and the device substrate. The dielectric layer laterally encloses the cavity. An anti-stiction layer lines the lower surface of the movable element. A method for manufacturing the MEMS package is also provided.

Abstract: A method for fusion bonding a pair of substrates together with silane preconditioning is provided. A surface of a first oxide layer or a surface of a second oxide layer is preconditioned with silane. The first and second oxide layers are respectively arranged on first and second semiconductor substrates. Water is applied to the surface of the first or second oxide layer. The surfaces of the first and second oxide layers are brought in direct contact. The first and second oxide layers are annealed. A method for manufacturing a microelectromechanical systems (MEMS) package using the fusion bonding is also provided.

Abstract: A method for fusion bonding a pair of substrates together with silane preconditioning is provided. A surface of a first oxide layer or a surface of a second oxide layer is preconditioned with silane. The first and second oxide layers are respectively arranged on first and second semiconductor substrates. Water is applied to the surface of the first or second oxide layer. The surfaces of the first and second oxide layers are brought in direct contact. The first and second oxide layers are annealed. A method for manufacturing a microelectromechanical systems (MEMS) package using the fusion bonding is also provided.